An integrated transformer arrangement for combining output signals of multiple differential power amplifiers to a single-ended load. The integrated transformer arrangement comprises a first transformer branch comprising an inductor loop. The inductor loop comprises a set of N windings connected in series. The first transformer branch further comprises a number of primary inductors. Each primary inductor comprises a winding placed concentrically to one winding of the inductor loop, and each primary inductor is configured to couple to a differential output of one of the multiple differential power amplifiers. The integrated transformer arrangement further comprises a secondary inductor comprising a winding placed concentrically to a winding of the inductor loop, and the secondary inductor is configured to couple to the single-ended load.

A bias circuit for a PA. A first transistor has its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal, a first current source connected to the first circuit node, and a first resistor connected between the first and second circuit nodes. A second transistor receives a first component of a differential input signal to the PA at its gate terminal, has its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal, and a third transistor receives a second component of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal. The gates terminals of the second and the third transistors are biased by a first voltage.

A differential power amplifier includes an input matching network, a first-stage amplification circuit, a first inter-stage matching network, a second-stage amplification circuit, a second inter-stage matching network, a third-stage amplification circuit, and an output matching network. The first-stage amplification circuit and the second-stage amplification circuit are single-ended input single-ended output circuits. The third-stage amplification circuit is a dual input dual output circuit. The second inter-stage matching network includes a first transformer T1, a first capacitor C1, a second capacitor C2, a first inductor L1, and a second inductor L2. The output matching network includes a second transformer T2. The inter-stage matching networks and the output matching network are realized by the first transformer T1 and the second transformer T2, which reduces an inter-stage matching difficulty, optimizes input return loss and gain, and improves output power.

This application provides a variable gain amplifier and a phased array transceiver, to enable the variable gain amplifier to keep a phase constant when switching a gain, and to enable a gain step to be stable with a frequency. The variable gain amplifier includes an amplification circuit, configured to amplify an input signal; a control circuit, configured to control a gain of the amplification circuit by adjusting an output current of the amplification circuit; and an inductive load and an inductive adjustment circuit, where the inductive load is coupled to a signal output end of the amplification circuit, the inductive adjustment circuit and the inductive load are inductively coupled, and the inductive adjustment circuit is adjustable.

A transformer device includes a first coil, a second coil, and a third coil. The first coil includes a first ring structure, a second ring structure, a first connecting portion, and a first terminal, in which the first terminal is arranged on the first connecting portion and is located at a central location between the first ring structure and the second ring structure, the first terminal is connected to the first ring structure through the first connecting portion in a first direction, and connected to the second ring structure through the first connecting portion in a second direction, and the first direction is the opposite of the second direction. The second coil is configured to couple the first ring structure. The third coil is configured to couple the second ring structure, in which the second coil and the third coil have the same structure.

A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N) of each of the stacked transistor units (112A, 112B, 112C).

A wide band matching network for power amplifier impedance matching, the wide band matching network comprising: a power amplifier transistor connected to an output network; the output network including: a series capacitor; an on-chip transformer connected to the capacitor in series, wherein the transformer and the capacitor act as a second order filter; and a port connected to the capacitor and a receiver switch.

MJC/ll

Disclosed is an amplifier having a carrier amplifier configured as a common-emitter carrier power stage and a peaking amplifier configured as a common-emitter peaking power stage. Further included is power adaptive biasing circuitry coupled between the carrier amplifier and the peaking amplifier, wherein the power adaptive biasing circuitry is configured to sense direct current base voltages of the common-emitter carrier power stage and to generate control currents that debias the common-emitter carrier power stage in response to the current base voltages of the common-emitter carrier power stage.

A radio-frequency (RF) apparatus includes a wideband receive (RX) impedance matching circuit to provide a received differential RF signal to RF receive circuitry. The wideband RX impedance matching circuit includes first and second inductors to receive the differential RF signal. The wideband RX impedance matching circuit further includes a third inductor coupled across an input o the RF receive circuitry. The third inductor performs the functionality of a capacitor having a negative capacitance value.

The present disclosure describes systems and devices for gain slope equalization in a radio frequency (RF) amplifier (200). The RF amplifier (200) may include an input stage (210) for receiving an RF signal. In conjunction with the input stage (210), the RF amplifier (200) may incorporate an amplification stage (215) to amplify the RF signal. Coupled with the amplification stage (215) may be a transformer (220) including a first winding to receive the amplified RF signal, a second winding providing an RF output signal, and a resonator including a third winding that is coupled to the first and second windings. The resonator may be coupled to a circuit network which may be tuned to affect the resonance frequency and the gain slope of the RF output signal.