Disclosed is a semiconductor integrated circuit device including: a switching transistor; a terminal to receive a control signal from outside; and a control circuit that controls the switching transistor based on the control signal. The control circuit includes: a reference voltage source that generates a reference voltage from the DC voltage; a differential amplifier to receive the reference voltage and a voltage of the voltage output terminal, and output a voltage applied to a control terminal of the switching transistor; and a logic circuit that generates a signal to control an operation state of the differential amplifier based on the control signal. According to an output signal of the logic circuit, the differential amplifier controls the switching transistor to be on in response to the control signal being a first logic level, and to be off in response to the control signal being a second logic level.

A small semiconductor device is provided. A semiconductor device with low power consumption is provided. A semiconductor device with a high degree of integration is provided. The semiconductor device includes a first transistor, an insulating layer over the first transistor, a conductive layer, and a gate driver; part of the conductive layer is provided to be embedded in the insulating layer; the gate driver includes a second transistor and a third transistor; the second transistor and the third transistor are stacked and provided over the first transistor; the second transistor and the third transistor each contain a metal oxide in a channel formation region; one of a source and a drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to a gate of the first transistor through the conductive layer; the gate driver is supplied with a first potential and a second potential; and the gate driver has a function of selecting the first potential or the second potential and supplying the selected potential to the gate of the first transistor.

Disclosed herein is an operational amplifier including a non-inverting input terminal, an inverting input terminal, a P-type metal oxide semiconductor input differential pair, a first input tail current source, an N-type metal oxide semiconductor input differential pair, a second input tail current source, an output stage, a first correction circuit, and a second correction circuit. The first correction circuit and the second correction circuit operate over an operation region of the P-type metal oxide semiconductor input differential pair, an operation region of the N-type metal oxide semiconductor input differential pair, and a transition region in which both the P-type metal oxide semiconductor input differential pair and the N-type metal oxide semiconductor input differential pair operate.

Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that enables fast switching between an on state bias voltage and an off state bias voltage for the power amplifier. The bias controller can transition a low impedance switch to an on state to electrically couple a first electrode of a charge holding capacitor to an input of the power amplifier. The charge holding capacitor can be pre charged with the on state bias voltage to quickly provide the on state bias voltage to the power amplifier. The bias controller can also transition the low impedance switch to an off state to couple the input of the power amplifier to the off state bias voltage.

An amplifier includes a power amplifier that amplifies an input signal, a VI detection circuit that is connected to a rear stage of the power amplifier to detect power of an output signal of the power amplifier, and a controller that turns on the power amplifier when the input signal is inputted to the power amplifier, turns off the power amplifier when the input signal is not inputted to the power amplifier, and turns on the power amplifier when the VI detection circuit detects a voltage that exceeds a predetermined value when the power amplifier is in off state.

A semiconductor device includes a differential amplification circuit that outputs differential output signals Vo1 and Vo2, external output terminals PD1 and PD2 to which one of the differential output signals Vo1 and Vo2 and single end signals Vo3 and Vo4 is selectively supplied, switch units SW1 and SW2 that control a conduction state between the external output terminal PD1 and the feedback line and a conduction state between the external output terminal PD2 and the feedback line, respectively, resistance elements R1 and R2 respectively provided in series with the switch units SW1 and SW2, a CMFB circuit that controls a common mode voltage of the differential amplification circuit according to a difference between an intermediate voltage Vcm of the external output terminals PD1 and PD2 in the feedback line and a reference voltage Vref, and a switch unit SW3 that controls to supply a clamp voltage to the feedback line.

A power amplifier that can support multiple communication networks while maintaining power efficiency across each of the supported communication networks is disclosed. In some implementations described herein, a power amplifier module includes a bypass circuit that enables different voltage supplies to be provided to the power amplifier. By regulating the voltage supply provided to the power amplifier, the power amplifier can support different communication networks while maintaining power efficiency across a dynamic frequency range. Moreover, embodiments herein may include a buck converter, or other form of DC-DC converter, that enables the power amplifier to operate with respect to multiple communication networks. Advantageously, in certain embodiments, because wireless devices that include multiple power amplifiers often require a DC-DC converter to support at least some of the communication networks, the inclusion of the buck converter in the embodiments described herein does not add additional cost or size to the wireless device.

Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that enables fast switching between an on state bias voltage and an off state bias voltage for the power amplifier. The bias controller can transition a low impedance switch to an on state to electrically couple a first electrode of a charge holding capacitor to an input of the power amplifier. The charge holding capacitor can be pre charged with the on state bias voltage to quickly provide the on state bias voltage to the power amplifier. The bias controller can also transition the low impedance switch to an off state to couple the input of the power amplifier to the off state bias voltage.

A bias circuit provides additional bias current for power amplifiers during data bursts to compensate for the gain droop caused by a rise in the power amplifier temperature during the data burst. A bias circuit includes a difference amplifier and switches coupled to the difference amplifier. The switches operate the bias circuit in a first mode when a transmit data burst is detected and operate the bias circuit in a second mode after the bias circuit has operated in the first mode for a predetermined period of time. In the first mode, the bias circuit charges a storage capacitor and sets an output current to zero. In the second mode, the bias circuit outputs the output current that increases above the initial value of zero as the PA warms up, where the excursion of this increase of current is determined by a register. The switches disable the bias circuit when the transmit data burst ends.

A method of operating a power amplifier supplying power to an antenna, supplying switched power to the power amplifier comprises in a first mode of operation via a driver circuit and one or more switches to switch the supply of power to the power amplifier on and off periodically; and calibrating the power amplifier in a second mode of operation. The calibrating comprises supplying voltage to the power amplifier via the same driver circuit and one or more switches for a calibration pulse duration longer than the on/off period. A power supply and an RF front end comprising the power supply are also disclosed.