H03F2203/7233

Source Switched Split LNA
20180302039 · 2018-10-18 ·

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

AMPLIFIER ARCHITECTURES WITH BYPASS CIRCUITS AND RESONANT STRUCTURES

The disclosed technology is related to a radio-frequency (RF) amplifier having a bypass circuit and a resonant structure to improve performance in a bypass mode (e.g., a low gain mode). The disclosed amplifiers have a resonant structure that effectively isolates an amplifier core from a bypass circuit. For example, in a bypass mode, the resonant structure is configured to create an open impedance looking into the amplifier core input. This effectively removes any loading from the amplifier core to the bypass circuit. The disclosed amplifiers with resonant structures improve linearity performance in bypass modes due at least in part to the open impedance to the amplifier core provided by the resonant structure.

Radio frequency front end transmit and receive path switch gain

A radio frequency front end of a user equipment for reducing power consumption includes a receive chain having a first low noise amplifier stage, a transmit chain including a first power amplifier stage, a transmit bypass path, a receive bypass path and a time division duplex switch. The transmit bypass path is selectively coupled to a transmit signal path at a first intermediate point of the transmit chain, prior to the first power amplifier stage. The receive bypass path is selectively coupled to a receive signal path at a first intermediate point of the receive chain after the first low noise amplifier stage. The time division duplex switch is selectively coupled to an antenna, the transmit bypass path, the receive bypass path, the first power amplifier stage and the first low noise amplifier stage.

RADIO FREQUENCY FRONT END TRANSMIT AND RECEIVE PATH SWITCH GAIN

A radio frequency front end of a user equipment for reducing power consumption includes a receive chain having a first low noise amplifier stage, a transmit chain including a first power amplifier stage, a transmit bypass path, a receive bypass path and a time division duplex switch. The transmit bypass path is selectively coupled to a transmit signal path at a first intermediate point of the transmit chain, prior to the first power amplifier stage. The receive bypass path is selectively coupled to a receive signal path at a first intermediate point of the receive chain after the first low noise amplifier stage. The time division duplex switch is selectively coupled to an antenna, the transmit bypass path, the receive bypass path, the first power amplifier stage and the first low noise amplifier stage.

Programmable impedance network in an amplifier

The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.

FRONT END CIRCUIT
20180205345 · 2018-07-19 · ·

A front end circuit includes a bypass circuit comprising a first bypass switch and a second bypass switch configured to bypass a signal to a first terminal according to switching operations of the first bypass switch and the second bypass switch; and an amplifier connected in parallel to the bypass circuit and configured to amplify the signal.

Front end circuit
09985586 · 2018-05-29 · ·

A front end circuit includes a bypass circuit comprising a first bypass switch and a second bypass switch configured to bypass a signal to a first terminal according to switching operations of the first bypass switch and the second bypass switch; and an amplifier connected in parallel to the bypass circuit and configured to amplify the signal.

Source Switched Split LNA
20240364269 · 2024-10-31 ·

A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.

Source switched split LNA
09973149 · 2018-05-15 · ·

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

HIGH-LINEARITY VARIABLE GAIN AMPLIFIER WITH BYPASS PATH

Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.