An amplifier circuit structure can include an amplifier located in a main path, and a first switch located in a bypass. One end of a second switch is a signal output end of the amplifier circuit structure, and the other end of the second switch is configured to selectively connect to a signal output end of the bypass or a signal output end of the main path. The first and second switches are configured to control their respective operating states when a first instruction is received, such that the main path is connected to the signal input end and the signal output end of the amplifier circuit structure; and to control their respective operating states when a second instruction is received, such that the bypass is connected to the signal input end of the amplifier circuit structure and the signal output end of the amplifier circuit structure.

A circuit chip with power supply noise rejection includes a switch unit, an energy storage unit, and an operating circuit. The switch unit has a first connection terminal and a second connection terminal. The first connection terminal is adapted to receive a power supply voltage. The switch unit is configured to selectively turn on a first connection path between the first connection terminal and the second connection terminal according to a clock signal. The energy storage unit is coupled to the second connection terminal. When the switch unit turns on the first connection path, the energy storage unit is configured to generate a storage voltage on the second connection terminal according to the power supply voltage. The operating circuit is coupled to the second connection terminal, and the operating circuit is configured to operate according to the storage voltage.

Methods and devices to improve nonlinearity performance of low noise amplifiers (LNAs) are disclosed. The described methods and devices reduce the capacitive loading of the LNA amplifying devices on the bypass path of the LNAs when operating in the bypass mode. This is performed by decoupling the active devices from ground to put the amplifying devices in a floating state, thus minimizing the impact of the gate-source capacitances of the amplifying devices on the overall linear performance of the LNA operating in the bypass mode.

An electric power conversion circuit includes: first and second input terminals; first and second output terminals; first and third switches connected to the first output terminal; second and fourth switches connected to the second output terminal; first through fourth diodes that are bridge-connected between the first and second switches; fifth through eighth diodes that are bridge-connected between the third and fourth switches; a first bootstrap circuit that is connected to control terminals of the second and fourth switches; and a second bootstrap circuit that is connected to control terminals of the first and third switches.

An amplification circuit includes a first switching circuit that includes input terminals and first and second output terminals and that puts the second output terminal into an open state with respect to the input terminals while selectively putting the first output terminal into a state of being connected to any of the input terminals or selectively puts the second output terminal into a state of being connected to any of input terminals while putting the first output terminal into a state of being open with respect to the input terminals; a matching network that is connected to the first output terminal; an amplifier that is connected to an output side of the matching network; a second switching circuit that is connected to an output side of the amplifier; and a bypass path that electrically connects the second output terminal and an output terminal of the second switching circuit. The amplifier is a variable-gain amplifier.

A front-end module (FEM) for a 6.1 GHz Wi-Fi acoustic wave resonator RF filter circuit. The device can include a power amplifier (PA), a 6.1 GHz resonator, and a diversity switch. The device can further include a low noise amplifier (LNA). The PA is electrically coupled to an input node and can be configured to a DC power detector or an RF power detector. The resonator can be configured between the PA and the diversity switch, or between the diversity switch and an antenna. The LNA may be configured to the diversity switch or be electrically isolated from the switch. Another 6.1 GHZ resonator may be configured between the diversity switch and the LNA. In a specific example, this device integrates a 6.1 GHz PA, a 6.1 GHZ bulk acoustic wave (BAW) RF filter, a single pole two throw (SP2T) switch, and a bypassable LNA into a single device.

An amplifier includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first transistor, a second transistor having a first terminal coupled to a second terminal of the first transistor, a third transistor having a first terminal coupled to a second terminal of the second transistor, a capacitor coupled between a control terminal and a second terminal of the third transistor, a bias circuit coupled to the first terminal of the third transistor for providing a bias voltage to the third transistor, a fourth transistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal for providing a bypass path, and a fifth transistor having a first terminal coupled to the first terminal of the first transistor and a second terminal coupled to the output terminal.

Apparatus and methods for power amplifiers with an injection-locked oscillator driver stage are provided herein. In certain configurations, a multi-mode power amplifier includes a driver stage implemented using an injection-locked oscillator and an output stage having an adjustable supply voltage that changes based on a mode of the multi-mode power amplifier. By implementing the multi-mode power amplifier in this manner, the multi-mode power amplifier exhibits excellent efficiency, including when the voltage level of the adjustable supply voltage is relatively low.

A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.

An amplifier circuit structure can include an amplifier located in a main path, and a first switch located in a bypass. One end of a second switch is a signal output end of the amplifier circuit structure, and the other end of the second switch is configured to selectively connect to a signal output end of the bypass or a signal output end of the main path. The first and second switches are configured to control their respective operating states when a first instruction is received, such that the main path is connected to the signal input end and the signal output end of the amplifier circuit structure; and to control their respective operating states when a second instruction is received, such that the bypass is connected to the signal input end of the amplifier circuit structure and the signal output end of the amplifier circuit structure.