A power limiting system and method for a low noise amplifier of a front end interface of a radio frequency communication device. A voltage regulator provides a source voltage to the low noise amplifier having a nominal voltage level that optimizes linearity of the low noise amplifier while a power level of a radio frequency input signal provided to an input of the low noise amplifier does not exceed a predetermined power level threshold. Detection circuitry detects when the power level of a radio frequency input signal exceeds the predetermined power level threshold and provides an adjust signal indicative thereof to the voltage regulator to reduce the source voltage below the nominal voltage level.

Apparatus and methods for front-end systems with directional couplers and a shared back switch are provided. In certain configurations, a method includes transmitting a first transmit signal from a first transmit port to an antenna port, generating a first coupled signal in response to the first transmit signal using a first directional coupler, providing the first coupled signal to a receive port by way of a first loopback selection switch and a shared back switch, transmitting a second transmit signal from a second transmit port to the antenna port, generating a second coupled signal in response to the second transmit signal using a second directional coupler, and providing the second coupled signal to the receive port by way of a second loopback selection switch and the shared back switch.

The present invention provides a detection circuit for a connection impedance and an electronic device. The detection circuit includes: a detection operational amplifier module, wherein the detection operational amplifier module includes: a first buffer, a switch unit, and a main operational amplifier; a first input terminal of the first buffer is connected to a first acquisition electrode through a first front-end circuit, an output terminal of the main operational amplifier is connected to a back-end circuit, and an output terminal of the first buffer is connected to a second input terminal of the first buffer; a first terminal of the switch unit is directly or indirectly connected to the first front-end circuit, and a second terminal of the switch unit is connected to the back-end circuit; and the switch unit is configured to: control the first front-end circuit to be directly connected to the back-end circuit, to form a straight-through channel.

A front-end module (FEM) for a 6.1 GHz Wi-Fi acoustic wave resonator RF filter circuit. The device can include a power amplifier (PA), a 6.1 GHz resonator, and a diversity switch. The device can further include a low noise amplifier (LNA). The PA is electrically coupled to an input node and can be configured to a DC power detector or an RF power detector. The resonator can be configured between the PA and the diversity switch, or between the diversity switch and an antenna. The LNA may be configured to the diversity switch or be electrically isolated from the switch. Another 6.1 GHZ resonator may be configured between the diversity switch and the LNA. In a specific example, this device integrates a 6.1 GHz PA, a 6.1 GHZ bulk acoustic wave (BAW) RF filter, a single pole two throw (SP2T) switch, and a bypassable LNA into a single device.

Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.

Methods and devices for processing of RF signals according to different gain modes are presented. According to one aspect, an active amplification mode is provided by switchable active paths coupled to respective input RF signals and a passive attenuation mode is provided by switchable passive paths coupled to the respective RF signals. According to another aspect, a common switchable feedback path coupled to the switchable active paths is used to provide an active attenuation mode. Coupling of the common switchable feedback path to the switchable active path is provided by switches of the switchable passive paths, including for coupling both ends of the common switchable feedback path or just one end.

Disclosed herein are signal amplifier architectures that provide a plurality of gain modes. Different gain modes can use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture can be configured to also provide targeted impedance in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture, improving the noise figure (NF), improving impedance matching, and eliminating the need for control logic associated with the degeneration block or matrix.

Disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture.

An amplification circuit includes a filter circuit, an amplifier, a capacitor, a bypass line, and a switch circuit that includes a first FET and a second FET connected in series between one end and the other end of the bypass line, a first resistance element connected in series to a gate of the first FET, and a second resistance element connected in series to a gate of the second FET. A first control signal is supplied to the gate of the first FET. A second control signal is supplied to the gate of the second FET. A product of a gate length and a gate width of the first FET and a resistance value of the first resistance element is smaller than a product of a gate length and a gate width of the second FET and a resistance value of the second resistance element.

An amplifier circuit includes a first terminal and a second terminal, an amplifier disposed in a first path connecting the first terminal and the second terminal, a first switch circuit disposed in the first path between the amplifier and the second terminal, an attenuator disposed in the first path between the amplifier and the first switch circuit, and a second switch circuit disposed in a second path that is connected to the first terminal and the second terminal while bypassing the amplifier, the attenuator, and the first switch circuit.