A calibration amplifier includes: a plurality of transistors and a variable resistor configured to change in response to clock pulses. During a calibration cycle, one of the plurality of transistors switches on in each calibration step based on a plurality of enable signals, and a gain of the calibration amplifier changes until an output voltage of the calibration amplifier exceeds a reference voltage and is set to a calibrated gain. The calibration amplifier outputs the output voltage by amplifying an input voltage using the calibrated gain.

A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.

An example method of operation may include identifying speakers and microphones connected to a network controlled by a controller, assigning a preliminary output gain to the speakers used to apply test signals, measuring ambient noise detected from the microphones, recording chirp responses from all microphones simultaneously based on the test signals, deconvolving all chirp responses to determine a corresponding number of impulse responses, and measuring average sound pressure levels (SPLs) of each of the microphones to obtain a SPL level based on an average of the SPLs.

Disclosed in the present invention are a radio frequency power amplifier, a radio frequency front-end module, and a communication terminal. The power amplifier includes a control unit, a power amplification unit, a detection and comparison unit, and a gain adjustment unit. According to a function relationship between the gain of the power amplification unit and the output power of the power amplification unit in different frequency bands and different power level modes, the control unit adjusts a function relationship between an adjustment current generated by the gain adjustment unit and a bias current of the power amplification unit; then the detection and comparison unit compares the bias current, of the power amplification unit with a reference current; according to the comparison result, the control unit controls whether the gain adjustment unit needs to generate an adjustment current and output the same to the power amplification unit.

A detection circuit for detecting a clock signal includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer outputs either a first signal or a second signal as a selection signal. The digital-to-analog converter outputs a reference voltage according to the selection signal. The comparator compares the clock signal to the reference voltage to generate a comparison signal. The counter counts a reference clock signal to generate an overflow signal, and resets the overflow signal according to the comparison signal. The overflow signal indicates the amplitude of the clock signal.

Provided are automatic level control (ALC) circuit, signal source, method for controlling signal source output power, and storage medium. The ALC circuit includes: at least two stages of ALC loops, each ALC loop including an amplifier, a coupler, a power detector, and an attenuation control module connected sequentially. An output end of an adjustable attenuator is connected to an input node of first stage of ALC loop; an output node of each stage of ALC loop, other than last stage of ALC loop, is connected to a normally on end of a two-way single-on switch, a first gating end of the two-way single-on switch is connected to an input node of a next stage of ALC loop, and the output node of the last stage of ALC loop and a second gating end of each two-way single-on switch are connected to an output end of the ALC circuit.

This application relates to audio driving circuitry (100), and in particular to audio driving circuitry for outputting first and second audio driving signals for driving a stereo audio load (106), which may be a stereo audio load of an accessory apparatus (102) removably coupled to the audio driving circuitry in use. A load monitor (111) is provided for monitoring to monitor, from a monitoring node (112), an indication of a common mode return current passing through a common return path, together with an indication of a common mode component of the first and second audio driving signals and to determine an impedance characteristic of the stereo audio load. The load monitor (111) can provide dynamic monitoring of any significant change in load impedance. In some embodiments the load monitor (111) comprises an adaptive filter (301) which adapts a parameter of the filter which is related to the load impedance so as to determine the indication of load impedance.

A modular vehicle sound system that can be upgraded or reconfigured by changing a plug-in module. In the advanced-capability embodiments the invention combines the functions of a vehicle data bus interface, a digital signal processor, and an amplifier. In the advanced-capability embodiments the invention provides a wireless interface with a separate digital device that can be used to control the inventive amplifier.

The present disclosure relates to circuitry for driving a piezoelectric transducer. The circuitry comprises amplifier circuitry configured to receive a drive signal and to output an output signal, based on the drive signal, to the piezoelectric transducer, a variable capacitor configured to be coupled in series with the piezoelectric transducer, and control circuitry. The control circuitry is configured to control a capacitance of the variable capacitor to compensate for hysteresis in the piezoelectric transducer and to control a gain of the amplifier circuitry to compensate for signal attenuation caused by the variable capacitor.

Polyphase power amplifiers for load insensitivity are disclosed. In certain embodiments, a polyphase transmit system includes an intermediate frequency transceiver including a first complex mixer that outputs a plurality of intermediate frequency transmit signals of different phases, and an intermediate frequency to radio frequency module including a second complex mixer that generates a plurality of radio frequency transmit signals of different phases based on the plurality of intermediate frequency transmit signals, and a polyphase power amplifier that receives the plurality of radio frequency transmit signals and outputs an amplified radio frequency signal. The polyphase transmit system further includes an antenna that transmits the amplified radio frequency signal.