According to some embodiments, an on-chip diplexer circuit is disclosed. The on-chip diplexer circuit includes a LC resonator module, the LC resonator module further comprises a first port, a first LC resonator unit and a second LC resonator unit; a first filter unit, the first filter unit is electrically connected to the first LC resonator unit in the LC resonator module, and the first filter unit is electrically connected to a second port; and a second filter unit, the second filter unit is electrically connected to the second LC resonator unit in the LC resonator module, and the second filter unit is electrically connected to a third port. According to some embodiments, the first LC resonator unit serves as an impedance matching circuit for a first signal having a first resonant frequency and serves as an open circuit for a second signal having a second resonant frequency that is different from the first resonant frequency; the second LC resonator unit serves as an impedance matching circuit for the second signal having the second resonant frequency and serves as an open circuit for the first signal having the first resonant frequency. The first filter unit passes signals with the first resonant frequency; and the second filter unit passes signals with the second resonant frequency.

An RF filter comprises a first substrate which in one embodiment is a plate including one or more exterior surfaces with a pattern of conductive material defining a plurality of capacitors. A second substrate which in one embodiment is a block includes one or more exterior surfaces with a pattern of conductive material defining a plurality of inductors. The block is seated on the plate in a relationship with the block normal to the plate and the capacitors coupled to the inductors respectively. In one embodiment, the capacitors comprise low impedance open ended capacitive RF signal transmission lines and the inductors comprise high impedance inductive RF signal transmission lines coupled to the low impedance capacitive RF signal transmission lines respectively to define transmission zeros.

Disclosed herein are methods and circuits that prevent energy that would produce a spurious resonance from lumped, distributed or waveguide circuit elements by using for example a low pass filter with a cut-off below the first spurious resonance frequency and bypassing the energy at frequencies at or above the first spurious resonance frequency through a secondary path. This secondary path is high pass in nature, with a cutoff substantially similar to the low pass filter. The two paths are combined at the common output, using a lowpass matching network.

A filter circuit may include a transmission line, a quarter wave resonator, and an electrical component coupled in series with the quarter wave resonator at a first end and to the transmission line at a second end. The electrical component may be have a frequency dependent impedance. The electrical component may be an inductor, a capacitor, or an inductor in series with a capacitor. In another aspect, a filter circuit may include a transmission line, a first quarter wave resonator coupled to a first electrical component and a second quarter wave resonator coupled to a second electrical component. Each of the first and second electrical components may be coupled to the transmission line in parallel with each other. The first and the second electrical components may have a frequency dependent impedance. The first electrical component may be the same as or different from the second electrical component.

A distributed LC filter structure is disclosed. The distributed LC filter structure provides simultaneously a distributed inductance and a distributed capacitance in the same structure. Accordingly, discrete passive elements are eliminated and high, homogenous integration is achieved. Interconnections between the distributed inductance and the distributed capacitance are tailored to leverage a parasitic inductance of the distributed capacitance to increase the overall inductance of the distributed LC filter structure. Similarly, the interconnections are tailored to leverage a parasitic capacitance resulting from the distributed inductance to add up with the distributed capacitance augmenting the overall capacitance of the structure.

A frequency multiplier (200) generates an output signal with a frequency 3 times of the input signal frequency. The frequency multiplier (200) comprises four cascaded stages. A first stage (201) is configured to receive an input signal and generate harmonics signals of the input signal. A second stage (202) is a passive filter, a frequency response of the passive filter has either a peak or a dip around an upper frequency end of a frequency band of the input signal. A third stage (203) is configured to mix the 1st and the 2nd order harmonics signals to generate 3rd order harmonic signals. A fourth stage (204) is configured to suppress the 1st and even-order harmonics signals and output a signal dominated with a frequency 3 times of the input signal frequency.

Fabrication of superconducting devices that combine or separate direct currents and microwave signals is provided. A method can comprise forming a direct current circuit that supports a direct current, a microwave circuit that supports a microwave signal, and a common circuit that supports the direct current and the microwave signal. The method can also comprise operatively coupling a first end of the direct current circuit and a first end of the microwave circuit to a first end of the common circuit. The direct current circuit can comprise a bandstop circuit and the microwave circuit can comprise a capacitor. Alternatively, the direct current circuit can comprise a bandstop circuit and the microwave circuit can comprise a bandpass circuit. Alternatively, the microwave circuit can comprise a capacitor and the direct current circuit can comprise one or more quarter-wavelength transmission lines.

According to some embodiments, an on-chip diplexer circuit is disclosed. The on-chip diplexer circuit includes a LC resonator module, the LC resonator module further comprises a first port, a first LC resonator unit and a second LC resonator unit; a first filter unit, the first filter unit is electrically connected to the first LC resonator unit in the LC resonator module, and the first filter unit is electrically connected to a second port; and a second filter unit, the second filter unit is electrically connected to the second LC resonator unit in the LC resonator module, and the second filter unit is electrically connected to a third port. According to some embodiments, the first LC resonator unit serves as an impedance matching circuit for a first signal having a first resonant frequency and serves as an open circuit for a second signal having a second resonant frequency that is different from the first resonant frequency; the second LC resonator unit serves as an impedance matching circuit for the second signal having the second resonant frequency and serves as an open circuit for the first signal having the first resonant frequency. The first filter unit passes signals with the first resonant frequency; and the second filter unit passes signals with the second resonant frequency.

A method and circuit are provided to reduce power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes series and shunt reactive circuit elements, such as series inductive reactance and a shunt inductive susceptance, configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network. Various implementations are provided, including single-ended, differential, multi-section, multi-output, and point-to-multi-point implementations, each with an optional low-speed mode switch.

A small-sized balance filter includes an unbalanced terminal and two pairs of balanced terminals and has a low signal insertion loss. An unbalanced terminal, a first balanced terminal including first and second terminals, and a second balanced terminal Rx including first and second terminals are provided. An unbalanced-side inductor is provided between the unbalanced terminal and the ground, first balanced-side inductors are provided between the first and second terminals of the first balanced terminal, second balanced-side inductors are provided between the first and second terminals of the second balanced terminal, and the unbalanced-side inductor is electromagnetic-field-coupled to each of the first and second balanced-side inductors.