First and second paths (I,II) are connected in parallel between an input terminal (IN) and an output terminal (OUT). A high-pass filter (HPF) is provided in the first path (I). A low-pass filter (LPF) is provided in the second path (II). A switch (SW1-SW4) connects one of the high-pass filter (HPF) and the low-pass filter (LPF) to the input terminal (IN) and the output terminal (OUT) and disconnects the other. A transmission line (TL1,TL2) is provided on the first and second paths (I,II) respectively. A line length of the transmission line (TL1,TL2) is adjusted such that a resonance caused due to circuit constants of the high-pass filter (HPF) and the low-pass filter (LPF) and capacitance obtained when the switch (SW1-SW4) is OFF is shifted to a communication frequency band.

A power combiner/divider circuit can be structured having a base structure with the addition of an odd-mode capacitor and a low pass network at an end of the base structure or structured having a base structure with the addition of an inductor and a high pass network at an end of the base structure. The power combiner/divider circuit can be implemented as a port coupled to multiple ports with low pass networks or high pass networks arranged at the ends of paths to the multiple ports. In embodiments using low pass base structures or low pass networks coupled to the base structures, inductors in such low pass sections can be positively coupled on a pair-wise basis.

A power combiner/divider circuit can be structured having a base structure with the addition of an odd-mode capacitor and a low pass network at an end of the base structure or structured having a base structure with the addition of an inductor and a high pass network at an end of the base structure. The power combiner/divider circuit can be implemented as a port coupled to multiple ports with low pass networks or high pass networks arranged at the ends of paths to the multiple ports. In embodiments using low pass base structures or low pass networks coupled to the base structures, inductors in such low pass sections can be positively coupled on a pair-wise basis.

A power combiner/divider circuit can be structured having a base structure with the addition of an odd-mode capacitor and a low pass network at an end of the base structure or structured having a base structure with the addition of an inductor and a high pass network at an end of the base structure. The power combiner/divider circuit can be implemented as a port coupled to multiple ports with low pass networks or high pass networks arranged at the ends of paths to the multiple ports. In embodiments using low pass base structures or low pass networks coupled to the base structures, inductors in such low pass sections can be positively coupled on a pair-wise basis.

A control circuit (16) is configured to detect the impedance P1 of a load (3) and control each of the reactance value L1 of a first variable reactance element (12), the reactance value L2 of a second variable reactance element (14), and the phase shift amount φ of a phase shifter (15) on the basis of the detected impedance P1. Consequently, impedance matching can be achieved even with the phase shifter (15) that performs discrete phase shift control.

A power combiner/divider circuit can be structured having a base structure with the addition of an odd-mode capacitor and a low pass network at an end of the base structure or structured having a base structure with the addition of an inductor and a high pass network at an end of the base structure. The power combiner/divider circuit can be implemented as a port coupled to multiple ports with low pass networks or high pass networks arranged at the ends of paths to the multiple ports. In embodiments using low pass base structures or low pass networks coupled to the base structures, inductors in such low pass sections can be positively coupled on a pair-wise basis.

A method for in-phase (I) and quadrature (Q) signal generation is disclosed. The method may include a first stage receiving a differential input signal. The first stage may also generate first differential in-phase and quadrature output signals, which may be sent by the first stage to a second stage. The second stage may generate second differential in-phase and quadrature output signals, which may have amplitude and phase mismatches less than an amplitude and phase mismatches of the first differential output signals. The second stage may then output the second differential I/Q output signals.

A phase shifter having both digital and analog shifting components is disclosed. The digital-analog phase shifter includes an input/output port configured, in part, for receiving an input radio frequency (RF) signal from an external source and outputting a phase shifted RF signal. A digital shifter performs coarse phase shifts of the input RF signal, while an analog shifter variably shift the phase of the input RF signal relative to the coarse phase shift. This produces a phase shifted RF signal having a total phase range that is output is continuously variable from 0 to 360.

A low loss, wide band, phase shifter utilizing one or more transformers in presented. In one case, the phase shifter includes a reflective SPDT switch that is coupled to a transformer. In another case, the phase shifter includes a distributed SPDT switch that includes switchable conduction paths having series connected unit elements of a same phase shift. The transformer may be part of an existing circuit and may be reused to provide the functionality of the phase shifter by introducing the reflective or the distributed SPDT switch.

A delay line includes one or more phase-shifting cells, where each phase-shifting cell includes a high-pass filter circuit that may be selectively coupled to or decoupled from a transmission line. The filter circuit is couplable in parallel with the transmission line and shifts a signal conveyed through the transmission line by a predetermined phase angle. The high-pass filter circuit includes one or more capacitors and one or more reactance elements (e.g., inductors). The selective coupling may be achieved using multi-gate transistors.