An embodiment of passive phase shifter comprises a ground shield, a pair of ground walls electrically connected to the ground shield having a first height above the ground shield; and a signal line positioned between the ground walls and electrically isolated from the ground shield. The signal line may comprise an intermediate signal line separated a second height above the ground shield; a top signal line separated from the intermediate signal line at a third height above the ground shield and electrically connected to the intermediate signal line by one or more conductive vias; and a plurality of blocks positioned between and electrically isolated from the intermediate signal line and the top signal line.

A wideband tunable frequency single-subband converter is proposed. The wideband frequency tunable converter operates within a wideband and tunable frequency range, and has process, voltage, and temperature (PVT) tracking capability. In one embodiment, the wideband converter comprises a frequency tunable polyphase filter having a plurality of switchable polyphase resistors. The polyphase resistors are controlled by a frequency tuning control signal to achieve wideband frequency tunability. In a preferred embodiment, a triode mode transistor is used as a polyphase resistor, and a different resistance value of the polyphase filter is realized by turning on one or multiple of the different transistors in triode mode. In addition, a constant Gm(R) bias generator is used to provide the gate biases to the triode mode transistors to maintain a constant and stable resistance value across PVT and other variation.

A wideband tunable frequency single-subband converter is proposed. The wideband frequency tunable converter operates within a wideband and tunable frequency range, and has process, voltage, and temperature (PVT) tracking capability. In one embodiment, the wideband converter comprises a frequency tunable polyphase filter having a plurality of switchable polyphase resistors. The polyphase resistors are controlled by a frequency tuning control signal to achieve wideband frequency tunability. In a preferred embodiment, a triode mode transistor is used as a polyphase resistor, and a different resistance value of the polyphase filter is realized by turning on one or multiple of the different transistors in triode mode. In addition, a constant Gm(R) bias generator is used to provide the gate biases to the triode mode transistors to maintain a constant and stable resistance value across PVT and other variation.

A phase shifter circuit and a power divider are disclosed. The phase shifter circuit provides a (90/N)-degree phase shift for a signal with two or more frequencies, where N is an integer. The phase shifter circuit includes a first inductor, a first capacitor, a second inductor and a second capacitor. The first inductor is grounded, and is coupled to the first capacitor in series. The second inductor is grounded, and is coupled to the second capacitor in series. A first node between the first capacitor and the first inductor is coupled to a node between a second node between the second capacitor and the second inductor. The power divider includes plural circuit blocks cascaded in series. Each circuit block provides a (90/N)-degree phase shift for a signal with two or more operating frequencies.

A phase shifter circuit and a power divider are disclosed. The phase shifter circuit provides a (90/N)-degree phase shift for a signal with two or more frequencies, where N is an integer. The phase shifter circuit includes a first inductor, a first capacitor, a second inductor and a second capacitor. The first inductor is grounded, and is coupled to the first capacitor in series. The second inductor is grounded, and is coupled to the second capacitor in series. A first node between the first capacitor and the first inductor is coupled to a node between a second node between the second capacitor and the second inductor. The power divider includes plural circuit blocks cascaded in series. Each circuit block provides a (90/N)-degree phase shift for a signal with two or more operating frequencies.

An electrically tunable radio frequency phase shifter with compact 3-D structure that integrates both ferromagnetic and ferroelectric materials, and utilizes 3-D structure to increase the tuning efficiency and achieve miniaturization.

An electrically tunable radio frequency phase shifter with compact 3-D structure that integrates both ferromagnetic and ferroelectric materials, and utilizes 3-D structure to increase the tuning efficiency and achieve miniaturization.

A phase shifter circuit and a power divider are disclosed. The phase shifter circuit provides a (90/N)-degree phase shift for a signal with two or more frequencies, where N is an integer. The phase shifter circuit includes a first inductor, a first capacitor, a second inductor and a second capacitor. The first inductor is grounded, and is coupled to the first capacitor in series. The second inductor is grounded, and is coupled to the second capacitor in series. A first node between the first capacitor and the first inductor is coupled to a node between a second node between the second capacitor and the second inductor. The power divider includes plural circuit blocks cascaded in series. Each circuit block provides a (90/N)-degree phase shift for a signal with two or more operating frequencies.

A phase shifter circuit and a power divider are disclosed. The phase shifter circuit provides a (90/N)-degree phase shift for a signal with two or more frequencies, where N is an integer. The phase shifter circuit includes a first inductor, a first capacitor, a second inductor and a second capacitor. The first inductor is grounded, and is coupled to the first capacitor in series. The second inductor is grounded, and is coupled to the second capacitor in series. A first node between the first capacitor and the first inductor is coupled to a node between a second node between the second capacitor and the second inductor. The power divider includes plural circuit blocks cascaded in series. Each circuit block provides a (90/N)-degree phase shift for a signal with two or more operating frequencies.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.