Described herein are systems and methods that allow for correcting a residual frequency offset in the GHz frequency range by using low-complexity analog circuit implementations of a broad-band frequency detector that comprises two analog polyphase filters in a dual configuration. Each filter comprises an RC network of cross-coupled capacitors that facilitate filters with opposite passbands and opposite stop-bands. In various embodiments, the outputs of the two filters are combined to obtain power metrics that when subtracted from each other, deliver a measure of the imbalance between the positive and negative halves of a frequency spectrum. Since the measure is substantially proportional to a frequency offset within a linear range spanning 5 GHz or more, the polyphase filters may be used in a broad-band frequency detector that, based on the measure, adjusts the frequency offset.

The invention relates to a phase sequencing three-phase network comprising a first side connected to a second side via the network. The first side comprises one endpoint (EP1) and the second side comprises three endpoints (EP2, EP3, and EP4). The network comprises five nodes (NP1-NP5) interconnected via feed line sections (FP1-FP10) comprising at least one transmission line section (R11-R102) each. The invention further relates to an optimization method for the network for deciding characteristic impedance and length of each transmission line section (R11-R102).

The invention relates to a phase sequencing three-phase network comprising a first side connected to a second side via the network. The first side comprises one endpoint (EP1) and the second side comprises three endpoints (EP2, EP3, and EP4). The network comprises five nodes (NP1-NP5) interconnected via feed line sections (FP1-FP10) comprising at least one transmission line section (R11-R102) each. The invention further relates to an optimization method for the network for deciding characteristic impedance and length of each transmission line section (R11-R102).

A clock generation circuit for generating a plurality of output clocks includes: a differential circuit for receiving a single input clock signal and outputting two differential clock signals, and a DC signal; a first polyphase filter for generating four clock signals from the differential clock signals which are a quadrature phase apart from each other; a plurality of setting buffers for setting a same DC point for the four clock signals and generating four resultant clock signals; coupled polyphase filters for generating four more clock signals which are a quadrature apart from each other, and outputting the resultant eight clock signals; a phase mixer, for generating eight output clock signals 45 degrees apart from each other; and a plurality of restoration buffers for setting a DC point for each of the eight clock signals and generating eight output clock signals all riding on a same DC point.

A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.

A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.

The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.

Described herein are systems and methods that allow for correcting a residual frequency offset in the GHz frequency range by using low-complexity analog circuit implementations of a broad-band frequency detector that comprises two analog polyphase filters in a dual configuration. Each filter comprises an RC network of cross-coupled capacitors that facilitate filters with opposite passbands and opposite stop-bands. In various embodiments, the outputs of the two filters are combined to obtain power metrics that when subtracted from each other, deliver a measure of the imbalance between the positive and negative halves of a frequency spectrum. Since the measure is substantially proportional to a frequency offset within a linear range spanning 5 GHz or more, the polyphase filters may be used in a broad-band frequency detector that, based on the measure, adjusts the frequency offset.

Described herein are systems and methods that allow for correcting a residual frequency offset in the GHz frequency range by using low-complexity analog circuit implementations of a broad-band frequency detector that comprises two analog polyphase filters in a dual configuration. Each filter comprises an RC network of cross-coupled capacitors that facilitate filters with opposite passbands and opposite stop-bands. In various embodiments, the outputs of the two filters are combined to obtain power metrics that when subtracted from each other, deliver a measure of the imbalance between the positive and negative halves of a frequency spectrum. Since the measure is substantially proportional to a frequency offset within a linear range spanning 5 GHz or more, the polyphase filters may be used in a broad-band frequency detector that, based on the measure, adjusts the frequency offset.

There is provided wireless transmitter that includes a poly phase filter (PPF) configured to receive an input differential intermediate frequency (IF) signal and to generate an in-phase differential IF signal and a quadrature differential IF signal. The wireless transmitter further includes a transformer-based circuit configured to receive an input differential local oscillator (LO) signal and to generate an in-phase differential LO signal and a quadrature differential LO signal based on the input differential LO signal. In addition, the wireless transmitter includes a mixer configured to multiplicatively mix the in-phase differential IF signal with the quadrature differential LO signal to produce a first RF signal component and to multiplicatively mix the quadrature differential IF signal with the in-phase differential LO signal to produce a second RF signal component, the mixer further configured to provide a differential RF signal comprising a (filtered or unfiltered) combination of the first RF signal component and the second RF signal component. Furthermore, the wireless transmitter includes an amplification stage configured to amplify the differential RF signal, the amplification stage comprising a driver stage and a power amplifier stage.