Apparatus and methods for quadrature combined Doherty amplifiers are provided herein. In certain embodiments, a separator is used to separate a radio frequency (RF) input signal into a plurality of input signal components that are amplified by a pair of Doherty amplifiers operating in quadrature. Additionally, a combiner is used to combine a plurality of output signal components generated by the pair of Doherty amplifiers, thereby generating an RF output signal exhibiting quadrature balancing.

Polyphase filters (PPFs) can be used to generate quadrature or other phase-shifted representations of an input signal provided to the PPF. In one approach, a “passive” polyphase filter can include a combination of resistive and capacitive elements. Such a topology can be referred to as an RC-PPF topology. Another passive circuit topology can be used to provide a PPF, by replacing the resistive elements with inductive elements, and by replacing the capacitive elements with resistive elements. A filter circuit can include cascaded RC-PPF and LR-PPF sections, such as in an alternating manner (e.g., an “RC-LR” topology). In this approach, a total insertion loss of cascaded LR-PPF and RC-PPF sections can be reduced as compared to using LR-PPF or RC-PPF sections, alone.

A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.

A wideband tunable frequency single-subband converter is proposed. The wideband frequency tunable converter operates within a wideband and tunable frequency range, and has process, voltage, and temperature (PVT) tracking capability. In one embodiment, the wideband converter comprises a frequency tunable polyphase filter having a plurality of switchable polyphase resistors. The polyphase resistors are controlled by a frequency tuning control signal to achieve wideband frequency tunability. In a preferred embodiment, a triode mode transistor is used as a polyphase resistor, and a different resistance value of the polyphase filter is realized by turning on one or multiple of the different transistors in triode mode. In addition, a constant Gm(R) bias generator is used to provide the gate biases to the triode mode transistors to maintain a constant and stable resistance value across PVT and other variation.

A wideband tunable frequency single-subband converter is proposed. The wideband frequency tunable converter operates within a wideband and tunable frequency range, and has process, voltage, and temperature (PVT) tracking capability. In one embodiment, the wideband converter comprises a frequency tunable polyphase filter having a plurality of switchable polyphase resistors. The polyphase resistors are controlled by a frequency tuning control signal to achieve wideband frequency tunability. In a preferred embodiment, a triode mode transistor is used as a polyphase resistor, and a different resistance value of the polyphase filter is realized by turning on one or multiple of the different transistors in triode mode. In addition, a constant Gm(R) bias generator is used to provide the gate biases to the triode mode transistors to maintain a constant and stable resistance value across PVT and other variation.

The invention relates to a phase sequencing three-phase network comprising a first side connected to a second side via the network. The first side comprises one endpoint (EP1) and the second side comprises three endpoints (EP2, EP3, and EP4). The network comprises five nodes (NP1-NP5) interconnected via feed line sections (FP1-FP10) comprising at least one transmission line section (R11-R102) each. The invention further relates to an optimization method for the network for deciding characteristic impedance and length of each transmission line section (R11-R102).

A temperature sensor using a poly-phase filter may include: a poly-phase filter suitable for receiving a divided clock, and having passive elements coupled to have one or more negative poles and one or more positive zeros; a comparator suitable for generating a reference clock by comparing potentials of first and second filter voltages outputted from the poly-phase filter; a phase frequency detector suitable for outputting an up or down signal by comparing the phase of the reference clock to the phase of a comparison clock; a current supply unit suitable for supplying and integrating a charge current under control of the up or the down signal; an oscillator suitable for outputting an oscillation signal; a divider suitable for generating the divided clock and the comparison clock; and a buffer suitable for inverting and non-inverting the divided clock and outputting the inverted and non-inverted divided clocks.

A method for in-phase (I) and quadrature (Q) signal generation is disclosed. The method may include a first stage receiving a differential input signal. The first stage may also generate first differential in-phase and quadrature output signals, which may be sent by the first stage to a second stage. The second stage may generate second differential in-phase and quadrature output signals, which may have amplitude and phase mismatches less than an amplitude and phase mismatches of the first differential output signals. The second stage may then output the second differential I/Q output signals.

A method for in-phase (I) and quadrature (Q) signal generation is disclosed. The method may include a first stage receiving a differential input signal. The first stage may also generate first differential in-phase and quadrature output signals, which may be sent by the first stage to a second stage. The second stage may generate second differential in-phase and quadrature output signals, which may have amplitude and phase mismatches less than an amplitude and phase mismatches of the first differential output signals. The second stage may then output the second differential I/Q output signals.

A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.