H03H7/21

Clock generation architecture using a poly-phase filter with self-correction capability
10963002 · 2021-03-30 · ·

An in-phase/quadrature (I/Q) clock generator is described. The I/Q clock generated includes a poly-phase filter configured to generate a four-phase quadrature clock signal in response to a two-phase quadrature clock signal generated in response to a single-ended input clock signal. The I/Q clock generated also includes a phase interpolator configured to generate an output four-phase quadrature clock signal from the four-phase quadrature clock signal. The I/Q clock generated further includes a poly-phase filter tune circuit coupled to an output of the phase interpolator. The poly-phase filter tune circuit is configured to generate a control voltage for the poly-phase filter to tune the four-phase quadrature clock signal from the poly-phase filter.

ULTRA-WIDE BAND FREQUENCY OFFSET ESTIMATION SYSTEMS AND METHODS FOR ANALOG COHERENT RECEIVERS
20210218383 · 2021-07-15 · ·

Described herein are systems and methods that allow for correcting a residual frequency offset in the GHz frequency range by using low-complexity analog circuit implementations of a broad-band frequency detector that comprises two analog polyphase filters in a dual configuration. Each filter comprises an RC network of cross-coupled capacitors that facilitate filters with opposite passbands and opposite stop-bands. In various embodiments, the outputs of the two filters are combined to obtain power metrics that when subtracted from each other, deliver a measure of the imbalance between the positive and negative halves of a frequency spectrum. Since the measure is substantially proportional to a frequency offset within a linear range spanning 5 GHz or more, the polyphase filters may be used in a broad-band frequency detector that, based on the measure, adjusts the frequency offset.

ULTRA-WIDE BAND FREQUENCY OFFSET ESTIMATION SYSTEMS AND METHODS FOR ANALOG COHERENT RECEIVERS
20210218383 · 2021-07-15 · ·

Described herein are systems and methods that allow for correcting a residual frequency offset in the GHz frequency range by using low-complexity analog circuit implementations of a broad-band frequency detector that comprises two analog polyphase filters in a dual configuration. Each filter comprises an RC network of cross-coupled capacitors that facilitate filters with opposite passbands and opposite stop-bands. In various embodiments, the outputs of the two filters are combined to obtain power metrics that when subtracted from each other, deliver a measure of the imbalance between the positive and negative halves of a frequency spectrum. Since the measure is substantially proportional to a frequency offset within a linear range spanning 5 GHz or more, the polyphase filters may be used in a broad-band frequency detector that, based on the measure, adjusts the frequency offset.

POLYPHASE FILTER
20210028769 · 2021-01-28 · ·

A first input terminal is connected to a point of connection of a drain terminal of a first transistor and a gate terminal of a fourth transistor. A second input terminal is connected to a point of connection of a drain terminal of a third transistor and a gate terminal of a second transistor. One of first through fourth output terminals to is connected to a source terminal of each of the first through fourth transistors to. A gate terminal of the first transistor and a drain terminal of the second transistor are connected, and a gate terminal of the third transistor and a drain terminal of the fourth transistor are connected.

POLYPHASE FILTER
20210028769 · 2021-01-28 · ·

A first input terminal is connected to a point of connection of a drain terminal of a first transistor and a gate terminal of a fourth transistor. A second input terminal is connected to a point of connection of a drain terminal of a third transistor and a gate terminal of a second transistor. One of first through fourth output terminals to is connected to a source terminal of each of the first through fourth transistors to. A gate terminal of the first transistor and a drain terminal of the second transistor are connected, and a gate terminal of the third transistor and a drain terminal of the fourth transistor are connected.

Phase shifter

A phase shifter capable of improving phase accuracy by a simple method is provided. The phase shifter includes a hybrid coupler circuit including inductors with mutual inductances, an amplifying circuit, an impedance matching circuit provided between the hybrid coupler circuit and the amplifying circuit. The impedance matching circuit includes a first resistance element connected to an output node of the hybrid coupler circuit, a capacitance element connected between the first resistance element and the ground line in series, another inductor connected in parallel with the first resistance element, and a second resistance element provided between the inductor and the ground line in series.

Phase shifter

A phase shifter capable of improving phase accuracy by a simple method is provided. The phase shifter includes a hybrid coupler circuit including inductors with mutual inductances, an amplifying circuit, an impedance matching circuit provided between the hybrid coupler circuit and the amplifying circuit. The impedance matching circuit includes a first resistance element connected to an output node of the hybrid coupler circuit, a capacitance element connected between the first resistance element and the ground line in series, another inductor connected in parallel with the first resistance element, and a second resistance element provided between the inductor and the ground line in series.

POLYPHASE FILTER
20200412339 · 2020-12-31 · ·

A first resistor to a fourth resistor and a first capacitor to a fourth capacitor are connected together in series in a ring shape. A first output terminal to a fourth output terminal are connected to series connection points between the first resistor to the fourth resistor and the first capacitor to the fourth capacitor, a first input terminal is connected to a series connection point between the fourth capacitor and the first resistor, and a second input terminal is connected to a series connection point between the second capacitor and the third resistor. Furthermore, a fifth resistor is connected between a series connection point between the first capacitor and the second resistor and a series connection point between the third capacitor and the fourth resistor.

QUADRATURE COMBINED DOHERTY AMPLIFIERS
20200382070 · 2020-12-03 ·

Apparatus and methods for quadrature combined Doherty amplifiers are provided herein. In certain embodiments, a separator is used to separate a radio frequency (RF) input signal into a plurality of input signal components that are amplified by a pair of Doherty amplifiers operating in quadrature. Additionally, a combiner is used to combine a plurality of output signal components generated by the pair of Doherty amplifiers, thereby generating an RF output signal exhibiting quadrature balancing.

APPARATUS AND METHODS FOR VECTOR MODULATOR PHASE SHIFTERS
20200382088 · 2020-12-03 ·

Apparatus and methods for vector modulator phase shifters are provided. In certain embodiments, a phase shifter includes a quadrature filter that filters a differential input signal to generate a differential in-phase (I) voltage and a differential quadrature-phase (Q) voltage, an in-phase variable gain amplifier (I-VGA) that amplifies the differential I voltage to generate a differential I current, a quadrature-phase variable gain amplifier (Q-VGA) that amplifies the differential Q voltage to generate a differential Q current, and a current mode combiner that combines the differential I voltage and the differential Q voltage to generate a differential output signal. A phase difference between the differential output signal and the differential input signal is controlled by gain settings of the I-VGA and the Q-VGA.