Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

A phase shifter (100) with controllable attenuation and a method for controlling the phase shifter is disclosed, the phase shifter (100) comprising a plurality of transmission line segments (120, 220) coupled in series, wherein each said transmission line segment (120, 220) comprises an attenuation circuit (130, 230), selectively couplable between a signal line (126, 222) of the transmission line segment (120, 220) and ground to selectively attenuate a signal propagating through the transmission line segment (120, 220). Each transmission line segment (120, 220) is switchable between a first configuration providing a first phase shift for a signal propagating through the transmission line segment (120, 220) and a second configuration providing a second phase shift, greater than said first phase shift, for a signal propagating through the transmission line segment (120, 220).

An attenuation circuit comprising: a connection-node for connecting to an RF connection; an isolation-capacitor connected in series between the connection-node and an internal-node; a first-bias-resistor connected in series between a first-control-node and the internal-node; a second-bias-resistor connected in series between the internal-node and a second-control-node; a first-attenuation-diode connected in series between the first-control-node and the internal-node, wherein the anode of the first-attenuation-diode is closest to the first-control-node; a second-attenuation-diode connected in series between the internal-node and the second-control-node, wherein the anode of the second-attenuation-diode is closest to the internal-node; a first-decoupling-capacitor connected in series between the first-control-node and the reference-node; and a second-decoupling-capacitor connected in series between the second-control-node and the reference-node.

A switch assembly includes a PIN diode connected between an antenna port and a receive port, a first shunt FET device connected between the receive port and ground, a first series FET device connected between the antenna port and a transmit port, a second shunt FET device connected between the transmit port and ground, and a plurality of bias control contacts configured to receive a corresponding plurality of bias control voltages to forward bias the first shunt FET device and the first series FET device into an ON state and to reverse bias the PIN diode and the second shunt FET device into an OFF state in a transmit mode, and to reverse bias the first shunt FET device and the first series FET device into the OFF state and to forward bias the PIN diode and the second shunt FET device into the ON state in a receive mode.

An attenuator circuit is provided. The attenuator circuit includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair. Further, the attenuator circuit includes a first plurality of resistive elements coupled in series between the first input node and a first output node for outputting a first output signal. The attenuator circuit additionally includes a second plurality of resistive elements coupled in series between the second input node and a second output node for outputting a second output signal. In addition, the attenuator circuit includes a shunt path coupled to a first intermediate node and a second intermediate node. The first intermedia node is arranged between two resistive elements of the first plurality of resistive elements. The second intermedia node is arranged between two resistive elements of the second plurality of resistive elements. The shunt path comprises a switch circuit configured to selectively couple the first intermediate node and the second intermediate node based on one or more control signals.

A signal level control element comprises a substrate having conductive formations defining a substrate integrated wave-guide arrangement disposed at least partly within the substrate; the substrate integrated waveguide arrangement providing a quadrature hybrid coupler having first and second pairs of signal ports, such that a signal introduced to a port of one pair of the first and second pairs is provided with equal amplitude but a 90 degree phase difference to both ports of the other pair of the first and second pairs; in which a port of the first pair is configured to receive an input signal and the other port of the first pair is configured to provide an output signal; and termination circuitry connected to the ports of the second pair, the termination circuitry providing, for each port of the second pair, a respective termination having a variable impedance dependent upon a respective control signal.

An ultrasound device, including a profile generator, an encoder configured to receive a profile signal from the profile generator, and an attenuator configured to receive a signal representing an output of an ultrasound sensor and coupled to the encoder to receive a control signal from the encoder, the attenuator including a plurality of attenuator stages, the attenuator configured to produce an output signal that is an attenuated version of the input signal.

In one embodiment, an RF impedance matching network for a plasma chamber is disclosed. The matching network includes an electronically variable capacitor (EVC) comprising discrete capacitors, each discrete capacitor having a corresponding switching circuit for switching in and out the discrete capacitor to alter a total capacitance of the EVC. Each switching circuit includes a diode operably coupled to the discrete capacitor to cause the switching in and out of the discrete capacitor, and a filter circuit parallel to the diode, the filter comprising a filtering capacitor in series with an inductor.

A magnetoresistive effect element includes: a first ferromagnetic layer; a second ferromagnetic layer; and a non-magnetic layer located between the first ferromagnetic layer and the second ferromagnetic layer, wherein a crystal structure of the non-magnetic layer is a spinel structure, wherein the non-magnetic layer contains Mg, Al, X, and O as elements constituting the spinel structure, and wherein the X is at least one or more elements selected from a group consisting of Ti, Pt, and W.

Provided is a compact digital attenuator. The compact digital attenuator includes a first attenuation cell to an nth attenuation cell, which include a plurality of attenuation cells connected to each other in parallel through a transmission line, wherein each of the plurality of attenuation cells may include a plurality of switch elements connected to each other in parallel, wherein the plurality of switch elements may be connected to the transmission line through one contact point.