A clock recovery circuit includes a first pulse circuit, a second pulse circuit, a state change circuit connected to the first pulse circuit and the second pulse circuit and a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit. The first pulse circuit receives data inputs to generate a first pulse signal. The second pulse circuit receives the data inputs to generate a second pulse signal. The state change circuit receives the first pulse signal and the second pulse signal and generate a first clock signal for a first transition of one of the data inputs in a first unit interval (UI). The first delay circuit receives the generated first clock signal and mask other transitions of the data inputs in the first UI.

A resonator and resonator method are provided. The resonator includes an inductor, a capacitor, and a switch configured to maintain energy in at least one of the inductor and the capacitor for a select period of time and to enable variability of energy in the at least one of the inductor and the capacitor for another period of time, to set a resonating frequency of the inductor and the capacitor.

A resonator and resonator method are provided. The resonator includes an inductor, a capacitor, and a switch configured to maintain energy in at least one of the inductor and the capacitor for a select period of time and to enable variability of energy in the at least one of the inductor and the capacitor for another period of time, to set a resonating frequency of the inductor and the capacitor.

In some examples, a delay apparatus includes a controllable delay line comprising a plurality of delay elements selectively connected in a signal path to vary a delay of a signal passing through the delay line, and a controllable phase shifter comprising reflective loads adjustable to vary a phase shift applied to the signal.

A resonator and resonator method are provided. The resonator includes an inductor, a capacitor, and a switch configured to maintain energy in at least one of the inductor and the capacitor for a select period of time and to enable variability of energy in the at least one of the inductor and the capacitor for another period of time, to set a resonating frequency of the inductor and the capacitor.

Systems, methods, and computer-readable media are disclosed for common mode filters with inverted inductive ground structures. In one embodiment, an example printed circuit board may have a first layer with a pair of differential transmission lines, and a common mode filter embedded in the printed circuit board. The common mode filter may include a signal reference structure and an inductive ground structure. The signal reference structure may include a first rectangular portion, and a second rectangular portion having the same dimensions. The second rectangular portion may be separated from the first rectangular portion by a distance. The inductive ground structure may include a first cell having a first conductive line coupled to a first side of the first rectangular portion and a first edge of the common mode filter, and a second cell having a second conductive line coupled to a first side of the second rectangular portion and the first edge.

Systems, methods, and computer-readable media are disclosed for common mode filters with inverted inductive ground structures. In one embodiment, an example printed circuit board may have a first layer with a pair of differential transmission lines, and a common mode filter embedded in the printed circuit board. The common mode filter may include a signal reference structure and an inductive ground structure. The signal reference structure may include a first rectangular portion, and a second rectangular portion having the same dimensions. The second rectangular portion may be separated from the first rectangular portion by a distance. The inductive ground structure may include a first cell having a first conductive line coupled to a first side of the first rectangular portion and a first edge of the common mode filter, and a second cell having a second conductive line coupled to a first side of the second rectangular portion and the first edge.

An analog time delay filter circuit including a first delay circuit block arranged in a modular layout, having a first time delay filter, a first input, a first output, and first and second pass-throughs; and a second delay circuit block arranged in the same modular layout, having a second time delay filter, a second input, a second output, and third and fourth pass-throughs.

An analog time delay filter circuit including a first delay circuit block arranged in a modular layout, having a first time delay filter, a first input, a first output, and first and second pass-throughs; and a second delay circuit block arranged in the same modular layout, having a second time delay filter, a second input, a second output, and third and fourth pass-throughs.

A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.