A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.

The disclosure disclosed herein provides a wireless power transmission device that wirelessly transmits power to electronic equipment coupled to a seat regardless of a position of the seat. According to an embodiment of the disclosure disclosed herein, a wireless power transmission device includes a power receiving unit coupled to a lower portion of a seat, and a power transmitting unit spaced apart from and below the power receiving unit, in which the power receiving unit is spaced apart from the power transmitting unit and slides into a moving direction of the seat, and the power receiving unit wirelessly receives power from the power transmitting unit and supplies power to electronic equipment installed in the seat.

According to an embodiment, a radio frequency delay line is described comprising a first conductor comprising a plurality of first inductors, a second conductor comprising a plurality of second inductors, wherein each of the plurality first inductors corresponds to a respective one of the plurality of second inductors and a plurality of inductor pairs, each inductor pair comprising a first inductor and the corresponding second inductor. For each of the plurality of inductor pairs, the first inductor and the corresponding second inductor are arranged so that an inductor area of the first inductor overlaps with an inductor area of the corresponding second inductor.

An apparatus includes a plurality of termination points and a clock mesh network. The termination points may be configured to send/receive timing signals. Each of the termination points may comprise an inductor. The clock mesh network may be configured to provide a path to transmit the timing signals from a clock source to a plurality of components and implement a condition using the inductors. The inductors for each of the termination points may be implemented to meet the condition. Values for the inductors may be determined based on characteristics of the clock mesh network. The condition may prevent power loss.

An apparatus includes a plurality of termination points and a clock mesh network. The termination points may be configured to send/receive timing signals. Each of the termination points may comprise an inductor. The clock mesh network may be configured to provide a path to transmit the timing signals from a clock source to a plurality of components and implement a condition using the inductors. The inductors for each of the termination points may be implemented to meet the condition. Values for the inductors may be determined based on characteristics of the clock mesh network. The condition may prevent power loss.

An apparatus for monitoring radio frequency (RF) signals is disclosed. The apparatus includes an RF splitter, a set of track-and-hold circuits, a set of analog-to-digital circuits (ADC) and a frequency tracking module. The RF splitter splits a set of incoming RF signals into multiple RF signal paths. Each of the track-and-hold circuits, which is clocked at a different frequency than others, samples the incoming RF signals from a respective one of the RF signal paths. Each of the ADCs receives the sampled data from a respective one of the track-and-hold circuits. Each of the ADCs is also clocked at same frequency as a corresponding one of the track-and-hold circuits. The frequency tracking module determines a frequency of the incoming RF signals.

A delay circuit for time offsetting an input radiofrequency signal, includes an all-pass filter having a given central frequency to linearize a phase-shift of an output signal relative to the input signal as a function of the frequency on a first frequency range; and first and second antiresonant circuits having respectively first and second central frequencies, the all-pass filter and the antiresonant circuits configured to linearize the phase-shift of the output signal relative to the input signal as a function of the frequency on a second frequency range including the first range. The difference between first and second central frequencies is less than 30% of the value of one of both frequencies, the difference between the first central frequency and the given central frequency of the all-pass filter is less than 30% of the value of a highest frequency between the first central frequency and the given central frequency.

A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.

A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.

A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.