Disclosed herein is a differential mode filter that includes first and second terminal electrodes provided on a first flange part of a core, and first and second wires wound around a winding core part of the core in an opposite direction to each other and connected respectively to the first and second terminal electrodes. The first and second wires cross each other on the winding core part to form a plurality of crossing portions that include first, second, and third crossing portions that are first, second, and third occurrences counting from the one end of the first and second wires, respectively. A first crossing angle between the first and second wires at the first crossing portion is larger than at least one of second and third crossing angles between the first and second wires at the second and third portions, respectively.

Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).

A balanced wideband impedance transformer can include a first conductor layer including a first metal line and a second metal line, a second conductor layer including a first feed line and disposed on the first conductor layer, a third conductor layer including a second feed line and disposed on the second conductor layer, and a fourth conductor layer including a third metal line and a fourth metal line, and disposed on the third conductor layer.

A high-order filter with a capacitive inner tapping technique is disclosed. The filter includes an inductor and a first resonant circuit including a first portion of the inductor and a first capacitor. The first resonant circuit is configured to attenuate first frequency components of an input signal above a cutoff frequency to generate a filtered signal. The filter further includes a second resonant circuit coupled in parallel with the first resonant circuit and including the first portion of the inductor and a second capacitor. The second resonant circuit is configured to attenuate the first frequency components of the input signal to generate the filtered signal. A third resonant circuit includes a second portion of the inductor and a third capacitor, wherein the third resonant circuit is configured to attenuate second frequency components of the filtered signal above the cutoff frequency to generate an output signal.

An apparatus is disclosed for current-mode filtering with switching. In an example aspect, the apparatus includes a filter including two input nodes, two output nodes, two differential paths, two bypass nodes respectively coupled between the two input nodes and the two output nodes along the two differential paths, a high-pass filter coupled between the two bypass nodes and the two output nodes, two low-pass switches, a band-pass switch, and a low-pass filter coupled in series with the high-pass filter along the two differential paths. The high-pass filter includes two series capacitors, which are respectively coupled between the two bypass nodes and the two output nodes, and two shunt inductors, which are respectively coupled to the two bypass nodes. The two low-pass switches are respectively coupled in parallel with the two series capacitors. The band-pass switch is coupled in series between the two shunt inductors.

An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first or second metal layers and coupled to one of the first or second plates in a resonant circuit.

Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.

An electronic device has an electronic device includes a substrate and a first dielectric layer over the substrate. The electronic device also includes a first metal layer on the first dielectric layer, the first metal layer including a first plate and a second dielectric layer over the first dielectric layer and the first metal layer. Additionally, the electronic device includes a second metal layer on the second dielectric layer. The second metal layer includes a second plate spaced apart from the first plate and a winding around the second plate.

A novel and useful adaptive antenna tuner and associated calibration mechanism for passive adaptive antenna matching networks. The tuner is suitable for use with cellular antennas and in one embodiment uses MEMS based tunable devices. The tuner contains voltage and current sensors inserted before the antenna matching network. The sensed complex impedance generates one or more update control signals for the tuning algorithm which drives the MEMS-based tunable devices.

Carrier aggregation systems and methods are disclosed. In some embodiments, a radio-frequency circuit can include a first signal path configured to present an approximately zero impedance to a first out-of-band signal that is out of a first frequency band. The radio-frequency circuit can further include a coupling circuit coupled to the first signal path and configured such that the approximately zero impedance presented by the first signal path to the first out-of-band signal results in the first out-of-band signal being substantially excluded from the first signal path. The radio-frequency circuit can further include a second signal path configured to present an approximately zero impedance to a second out-of-band signal that is out of a second frequency band.