A radio frequency (RF) transmission circuit includes an input stage, a current-mode mixer coupled to an output of the input stage, an attenuator coupled to an output of the current-mode mixer, and a matching network coupled to an output of the attenuator. The input stage, current-mode mixer, attenuator, and the matching network are configured in a series stack.

A radio frequency (RF) transmission circuit includes an input stage, a current-mode mixer coupled to an output of the input stage, an attenuator coupled to an output of the current-mode mixer, and a matching network coupled to an output of the attenuator. The input stage, current-mode mixer, attenuator, and the matching network are configured in a series stack.

A communication system includes a transmitter configured to transmit a modulated signal, a transmission line configured to carry the modulated signal, and a receiver coupled to the transmitter by the transmission line, and configured to receive the modulated signal. The transmitter includes a modulator configured to generate the modulated signal responsive to a data signal and a carrier signal. The receiver includes a demodulator configured to demodulate the modulated signal responsive to a first carrier signal. The demodulator includes a filter and a gain adjusting circuit configured to adjust a gain of the filter, and to generate the set of control signals based on a voltage of the filtered first signal and a voltage of the first signal. The gain adjusting circuit includes a first peak detector coupled to the filter, and configured to detect a peak value of the voltage of the filtered first signal.

A low pass filter is disclosed. In an embodiment a low-pass filter includes a current-compensated choke, a reference potential and a capacitor connected in parallel with the current-compensated choke and to the reference potential, wherein a core of the current-compensated choke is configured to have a magnetic circuit, and wherein the core has an air gap.

A glitch filter is provided. The glitch filter receives an input signal and sets a voltage level of an intermediary input node in accordance with a state of the input signal. The glitch filter charges or discharges a switched capacitance based on the voltage level of the intermediary input node and charges or discharges a filter capacitance based on a charge of the switched capacitance. The glitch filter sets a state of an output signal based on the charge of the filter capacitance. The glitch filter includes a reset stage that at least partially filters a burst of glitches in the input signal from the output signal by controlling the charge of the switched capacitance based on the state of the input signal and the state of the output signal.

A glitch filter is provided. The glitch filter receives an input signal and sets a voltage level of an intermediary input node in accordance with a state of the input signal. The glitch filter charges or discharges a switched capacitance based on the voltage level of the intermediary input node and charges or discharges a filter capacitance based on a charge of the switched capacitance. The glitch filter sets a state of an output signal based on the charge of the filter capacitance. The glitch filter includes a reset stage that at least partially filters a burst of glitches in the input signal from the output signal by controlling the charge of the switched capacitance based on the state of the input signal and the state of the output signal.

The technology relates to quantum computing devices and test arrangements for detecting information from the qubits of such devices. According to aspects of the technology, a Purcell filter is structured in a multi-pole architecture to provide a sharper filter response having a flatter signal pass band, sharper turn-off skirt, and enhanced out of band rejection. The system is able to determine the states of the qubits by detecting the frequency of the readout resonators of the test arrangement. The Purcell filter is configured to be sharply tuned to enable faster readout to avoid issues associated with a longer relaxation time (T1) of the qubits.

The technology relates to quantum computing devices and test arrangements for detecting information from the qubits of such devices. According to aspects of the technology, a Purcell filter is structured in a multi-pole architecture to provide a sharper filter response having a flatter signal pass band, sharper turn-off skirt, and enhanced out of band rejection. The system is able to determine the states of the qubits by detecting the frequency of the readout resonators of the test arrangement. The Purcell filter is configured to be sharply tuned to enable faster readout to avoid issues associated with a longer relaxation time (T1) of the qubits.

This electronic notch filter is able to receive an input signal and deliver a filtered signal having an amplitude, at a cut-off frequency, that is attenuated with respect to that of the input signal. It comprises a module for integrating the input signal during several successive time windows, each time window starting at a respective initial time instant and having a duration substantially equal to the inverse of the cut-off frequency, the initial temporal time instants of at least two distinct windows being separated by a temporal shift of a value greater than or equal to a predefined reference duration, each integration of the input signal during a respective temporal window resulting in a respective intermediate signal; and a module for summing the intermediate signals coming from the integration module; the filtered signal depending on the sum of said intermediate signals.

A temperature-compensated low-pass filter includes a differential amplifier that controls a first transistor to pass a subthreshold current through the transistor to charge a capacitor with low-pass-filtered output voltage. A second transistor has a first terminal coupled to an input terminal of the low-pass filter and has a second terminal coupled to a current source conducting a bias current. The differential amplifier also controls the second transistor to conduct the bias current responsive to a difference between a complementary-to-absolute-temperature reference voltage and a voltage of the second terminal of the second transistor.