In a phase adjustment circuit, a binary circuit is configured to output a binary signal on the basis of an edge of a video signal. A phase-delayed clock signal generation circuit is configured to generate a phase-delayed clock signal having a later phase than a phase of a clock signal by a first delay amount. A delay time control circuit is configured to cause a phase of the binary signal and the phase of the phase-delayed clock signal to match each other by adjusting the first delay amount. A sampling signal generation circuit is configured to generate a sampling signal having a later phase than the phase of the clock signal by a second delay amount. The second delay amount is in accordance with both a phase shift amount, which is based on the clock signal, and the first delay amount.

In a phase adjustment circuit, a binary circuit is configured to output a binary signal on the basis of an edge of a video signal. A phase-delayed clock signal generation circuit is configured to generate a phase-delayed clock signal having a later phase than a phase of a clock signal by a first delay amount. A delay time control circuit is configured to cause a phase of the binary signal and the phase of the phase-delayed clock signal to match each other by adjusting the first delay amount. A sampling signal generation circuit is configured to generate a sampling signal having a later phase than the phase of the clock signal by a second delay amount. The second delay amount is in accordance with both a phase shift amount, which is based on the clock signal, and the first delay amount.

Methods and apparatus for implementing a phase shifter in a space, e.g., chip surface area, efficient manner is described. In various embodiments a combination of switches, capacitors and a transformer are used in combination as a controllable phase shifter. In some embodiments the phase shifter supports a phase shift of 0 degrees or 180 degrees depending on the position of one or more switches. The mutual inductance of the transformer in at least some embodiments emulates one or more capacitors in a phase shift network making for an implementation that can be implemented on a semiconductor in an area efficient manner as compared to implementations using more capacitors and independent inductors.

Methods and apparatus for implementing a phase shifter in a space, e.g., chip surface area, efficient manner is described. In various embodiments a combination of switches, capacitors and a transformer are used in combination as a controllable phase shifter. In some embodiments the phase shifter supports a phase shift of 0 degrees or 180 degrees depending on the position of one or more switches. The mutual inductance of the transformer in at least some embodiments emulates one or more capacitors in a phase shift network making for an implementation that can be implemented on a semiconductor in an area efficient manner as compared to implementations using more capacitors and independent inductors.

A transmitter apparatus that performs beamforming with phase correction uses power detectors present between power amplifiers (PAs) and antennas are used to measure power amplitudes on at least two transmission paths. The sum and difference of these amplitudes are then evaluated to determine a phase difference therebetween. A phase of one signal contributing to the sum and difference may be modified until the sum and difference are the same. Based on an amount of phase modification, a correction signal may be sent to a beamforming circuit to provide phase correction during beamforming.

A transmitter apparatus that performs beamforming with phase correction uses power detectors present between power amplifiers (PAs) and antennas are used to measure power amplitudes on at least two transmission paths. The sum and difference of these amplitudes are then evaluated to determine a phase difference therebetween. A phase of one signal contributing to the sum and difference may be modified until the sum and difference are the same. Based on an amount of phase modification, a correction signal may be sent to a beamforming circuit to provide phase correction during beamforming.

Switch circuits for electrical power are formed of a hybrid coupler configured to receive a signal as an input, and output first and second pulsed wave signals along first and second signal paths, respectively; in a plurality of time frames, wherein the phases of the first and second pulsed wave signals along first and second signal paths are aligned. The switch circuits may be incorporated in time folding power circuits as an exemplary application.

Switch circuits for electrical power are formed of a hybrid coupler configured to receive a signal as an input, and output first and second pulsed wave signals along first and second signal paths, respectively; in a plurality of time frames, wherein the phases of the first and second pulsed wave signals along first and second signal paths are aligned. The switch circuits may be incorporated in time folding power circuits as an exemplary application.

Apparatus and methods for phase shifting are provided herein. In certain embodiments, a phase shifter includes a first port, a first controllable reflective load, a second port, a second controllable reflective load, and a pair of coupled lines that are electromagnetically coupled to one another. The pair of coupled lines includes a first conductive line between the first port and the first controllable reflective load and a second conductive line between the second controllable reflective load and the second port. At least one of the first controllable reflective load or the second controllable reflective load includes a switched transmission line load.

Apparatus and methods for phase shifting are provided herein. In certain embodiments, a phase shifter includes a first port, a first controllable reflective load, a second port, a second controllable reflective load, and a pair of coupled lines that are electromagnetically coupled to one another. The pair of coupled lines includes a first conductive line between the first port and the first controllable reflective load and a second conductive line between the second controllable reflective load and the second port. At least one of the first controllable reflective load or the second controllable reflective load includes a switched transmission line load.