A digital phase shifter includes a plurality of digital phase shift circuit groups in which a plurality of digital phase shift circuits are connected in cascade and one or more bend-type connection units connected between two digital phase shift circuit groups. At least one of the digital phase shift circuits constituting at least one digital phase circuit group is a mitigation circuit that mitigates a distribution of phase shift amounts.

This application provides a semiconductor switch device and a preparation method thereof, and a solid-state phase shifter. The semiconductor switch device includes a second semiconductor layer, a first intrinsic layer, a first semiconductor layer, a second intrinsic layer, and a third semiconductor layer that are stacked in a sandwich structure. The first intrinsic layer is located between the second semiconductor layer and the first semiconductor layer, and the first intrinsic layer, the second semiconductor layer, and the first semiconductor layer form a first PIN diode. The second intrinsic layer is located between the third semiconductor layer and the first semiconductor layer, and the second intrinsic layer, the third semiconductor layer, and the first semiconductor layer form a second PIN diode. The first PIN diode and the second PIN diode are axisymmetrically disposed.

This application provides a semiconductor switch device and a preparation method thereof, and a solid-state phase shifter. The semiconductor switch device includes a second semiconductor layer, a first intrinsic layer, a first semiconductor layer, a second intrinsic layer, and a third semiconductor layer that are stacked in a sandwich structure. The first intrinsic layer is located between the second semiconductor layer and the first semiconductor layer, and the first intrinsic layer, the second semiconductor layer, and the first semiconductor layer form a first PIN diode. The second intrinsic layer is located between the third semiconductor layer and the first semiconductor layer, and the second intrinsic layer, the third semiconductor layer, and the first semiconductor layer form a second PIN diode. The first PIN diode and the second PIN diode are axisymmetrically disposed.

A method comprises activating an interval timer to expire in a calibration time interval and, in response to the timer expiring, performing an impedance analysis of an electronic network. The impedance analysis can use time-domain reflectometry. Based on the analysis, the method can calibrate a variable impedance device to have a first impedance and re-activate the timer. The method can perform a second impedance analysis based on calibrating the variable impedance device. The method can include determining a drift rate and modifying the calibration time interval. The variable impedance device can comprise a phase-change material (PCM), and the time interval can correspond to a retention time of the PCM and/or a dynamic drift rate. A system comprising a segment of an electronic network, a timer, a variable impedance device, and an impedance tuning system can embody operations of the method.

A method comprises activating an interval timer to expire in a calibration time interval and, in response to the timer expiring, performing an impedance analysis of an electronic network. The impedance analysis can use time-domain reflectometry. Based on the analysis, the method can calibrate a variable impedance device to have a first impedance and re-activate the timer. The method can perform a second impedance analysis based on calibrating the variable impedance device. The method can include determining a drift rate and modifying the calibration time interval. The variable impedance device can comprise a phase-change material (PCM), and the time interval can correspond to a retention time of the PCM and/or a dynamic drift rate. A system comprising a segment of an electronic network, a timer, a variable impedance device, and an impedance tuning system can embody operations of the method.

A first switch is connected in parallel with a circuit element. A second switch is connected in series with a parallel circuit constituted by the circuit element and the first switch. The first switch and the second switch alternately perform on-off operation.

A first switch is connected in parallel with a circuit element. A second switch is connected in series with a parallel circuit constituted by the circuit element and the first switch. The first switch and the second switch alternately perform on-off operation.

The signal strength of a vector modulator based phase shifter can be increased enabling signals to be received or transmitted over larger distances than existing phase shifters by applying multiple weights to components of a signal. An input signal can be divided into orthogonal components that can be weighted and combined to generate an intermediate signal. A second intermediate signal can be generated by applying complementary weights to the orthogonal component signal. The two intermediate signals can be combined to obtain the phase shifted signal. By combining complementary weighted component signals, a phase shifted signal with improved signal to noise ratio and greater signal strength can be generated.

The signal strength of a vector modulator based phase shifter can be increased enabling signals to be received or transmitted over larger distances than existing phase shifters by applying multiple weights to components of a signal. An input signal can be divided into orthogonal components that can be weighted and combined to generate an intermediate signal. A second intermediate signal can be generated by applying complementary weights to the orthogonal component signal. The two intermediate signals can be combined to obtain the phase shifted signal. By combining complementary weighted component signals, a phase shifted signal with improved signal to noise ratio and greater signal strength can be generated.

A hybrid coupler operating in a power divider mode includes two inputs, two outputs, a capacitive module coupled between the inputs and the outputs or on each input and each output. The capacitive module has an adjustable capacitive value making it possible to adjust the central frequency. A calibration method includes: delivering a first reference signal having a first reference frequency on the first input of the hybrid coupler, measuring the peak value of a first signal delivered to the first output of the coupler and measuring the peak value of a second signal delivered to the second output of the coupler. The two peak values are compared and an adjustment of the capacitive value of the capacitive module is made until an equality of the peak values is obtained to within a tolerance.