Monolithic attenuator, limiter, and linearizer circuitry to be integrated with other circuitry on a chip are provided. According to one aspect, a monolithic attenuator and limiter circuit comprises an input terminal, an output terminal, a first resistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal, and a second resistor having a first terminal coupled to the first or second terminal of the first resistor and a second terminal coupled to ground. At least the first resistor is a non-linear resistor whose resistance changes as a function of the voltage across the resistor. The monolithic attenuator and limiter circuit may be part of a “Pi” or “Tee” topology. According to another aspect, a non-linear shunt resistor coupled to the input of an amplifier circuit can operate to linearize the gain of the amplifier circuit over a range of input levels.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

A multi-chip module is provided including a multiplier configured to multiply a frequency of an input signal into a predetermined Ka-band frequency center channel, a modulator configured to modulate the center channel, and an amplifier configured to amplify a modulated signal for output.

A phase shifter (100) with controllable attenuation and a method for controlling the phase shifter is disclosed, the phase shifter (100) comprising a plurality of transmission line segments (120, 220) coupled in series, wherein each said transmission line segment (120, 220) comprises an attenuation circuit (130, 230), selectively couplable between a signal line (126, 222) of the transmission line segment (120, 220) and ground to selectively attenuate a signal propagating through the transmission line segment (120, 220). Each transmission line segment (120, 220) is switchable between a first configuration providing a first phase shift for a signal propagating through the transmission line segment (120, 220) and a second configuration providing a second phase shift, greater than said first phase shift, for a signal propagating through the transmission line segment (120, 220).

An apparatus includes a radio frequency (RF) input port, an RF output port, a variable attenuation network, a first filter network, a second filter network, and a third filter network. The variable attenuation network may be coupled between the RF input port and the RF output port. Attenuation of the variable attenuation network is controlled by a first control signal and a second control signal. The first filter network may be connected between the RF input port and the RF output port. The second filter network may be connected between the variable attenuation network and a ground potential. The third filter network may be connected between the variable attenuation network and the ground potential. The first, the second, and the third filter networks modify performance of the variable attenuation network to produce a particular tilt of a radio frequency signal passing through the apparatus between the RF input port and the RF output port. The particular tilt is selectable by adjustment of at least one of the first and the second control signals.

A method includes providing a resonant attenuation circuit comprising a first active shorting device connected to a proximal end of an inductive element and a second active shorting device connected to a distal end of the inductive element. The method also includes providing a first control signal to the first active shorting device that places the first active shorting device in a region of operation where incremental increases or decreases in voltage change a shorting impedance of the second active shorting device. A signal attenuator includes a signal propagation path and a plurality of shorting units sequentially attached to the signal propagation path and a control circuit configured to control a level of attenuation provided by each shorting unit. The control circuit and a corresponding method activates subsequent shorting units only if all previous shorting units are at least partially activated.

A method includes providing a resonant attenuation circuit comprising a first active shorting device connected to a proximal end of an inductive element and a second active shorting device connected to a distal end of the inductive element. The method also includes providing a first control signal to the first active shorting device that places the first active shorting device in a region of operation where incremental increases or decreases in voltage change a shorting impedance of the second active shorting device. A signal attenuator includes a signal propagation path and a plurality of shorting units sequentially attached to the signal propagation path and a control circuit configured to control a level of attenuation provided by each shorting unit. The control circuit and a corresponding method activates subsequent shorting units only if all previous shorting units are at least partially activated.

An attenuation circuit with a low insertion loss is provided. The attenuation circuit includes an input to receive an input signal, an output to provide an attenuated signal, an attenuator coupled between the input and the output, the attenuator being configured to attenuate the input signal, an isolation switch constructed to isolate the attenuator from the input or the output when in a bypass mode, and a bypass switch coupled in parallel with the attenuator to couple the input to the output when in the bypass mode.

Provided herein are apparatus and methods for high linearity voltage variable attenuators (VVAs). In certain configurations, a high linearity VVA includes multiple shunt arms or circuits that operate in parallel with one another between a signal node and a first DC voltage, such as ground. Thus, the shunt arms are in shunt with respect to a signal path of the VVA. The multiple shunt arms include a first shunt arm of one or more n-type field effect transistor (NFETs) and a second shunt arm of one or more p-type field effect transistor (PFETs). The gates of the NFETs are controlled using a control voltage, and the gates of the PFETs are controlled using a complementary control voltage that changes inversely with respect to the control voltage.