Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.

A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

A group delay compensation filter includes: a waveguide that has a first slot and that is configured to transmit a signal; and a first dielectric resonator that includes: a first dielectric, a first metal layer formed over a surface of the first dielectric, and a first opening provided in the first metal layer, wherein the first dielectric resonator is in contact with the waveguide with the first opening coupled to the first slot, and wherein the first dielectric resonator is configured to compensate group delay in a first frequency band of the signal.

A group delay compensation filter includes: a waveguide that has a first slot and that is configured to transmit a signal; and a first dielectric resonator that includes: a first dielectric, a first metal layer formed over a surface of the first dielectric, and a first opening provided in the first metal layer, wherein the first dielectric resonator is in contact with the waveguide with the first opening coupled to the first slot, and wherein the first dielectric resonator is configured to compensate group delay in a first frequency band of the signal.

A system includes an electric motor, at least one pair of high side and low side switches connected to the electric motor, and a microcontroller connected to the high side and low side switches. At least the low side switches have a minimum on-time requirement. The microcontroller controls the switches by outputting a pulse-width modulation (PWM) signal. At least the PWM signal outputted to the low side switch is center-aligned to the off-time. When a request is made to the microcontroller resulting in a low side on-time of zero with a previous duty cycle request that is greater than a predetermined threshold, the microcontroller is constructed and arranged to extend the duty cycle of the low side switch of the at least one pair of switches into the next period to a duration of the required minimum on-time.

A method comprises activating an interval timer to expire in a calibration time interval and, in response to the timer expiring, performing an impedance analysis of an electronic network. The impedance analysis can use time-domain reflectometry. Based on the analysis, the method can calibrate a variable impedance device to have a first impedance and re-activate the timer. The method can perform a second impedance analysis based on calibrating the variable impedance device. The method can include determining a drift rate and modifying the calibration time interval. The variable impedance device can comprise a phase-change material (PCM), and the time interval can correspond to a retention time of the PCM and/or a dynamic drift rate. A system comprising a segment of an electronic network, a timer, a variable impedance device, and an impedance tuning system can embody operations of the method.