A group delay compensation filter includes: a waveguide that has a first slot and that is configured to transmit a signal; and a first dielectric resonator that includes: a first dielectric, a first metal layer formed over a surface of the first dielectric, and a first opening provided in the first metal layer, wherein the first dielectric resonator is in contact with the waveguide with the first opening coupled to the first slot, and wherein the first dielectric resonator is configured to compensate group delay in a first frequency band of the signal.

A group delay compensation filter includes: a waveguide that has a first slot and that is configured to transmit a signal; and a first dielectric resonator that includes: a first dielectric, a first metal layer formed over a surface of the first dielectric, and a first opening provided in the first metal layer, wherein the first dielectric resonator is in contact with the waveguide with the first opening coupled to the first slot, and wherein the first dielectric resonator is configured to compensate group delay in a first frequency band of the signal.

An apparatus including a memory subsystem. The memory subsystem includes a data input and a clock input. The apparatus also includes a variable delay circuit coupled to one of the data input or the clock input. Additionally, the apparatus includes a controller coupled to the variable delay circuit. The controller is configured to dynamically control the delay of the variable delay circuit. The controller may adjust the delay of the variable delay circuit based on at least one of timing data for a memory subsystem design of the memory subsystem, timing data for the memory subsystem, a voltage applied to the memory subsystem, or a temperature of the memory subsystem.

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

The present disclosure provides an analog counter circuit for use in a minimal-sized circuitry. The analog counter circuit of the present disclosure can provide much higher resolution versus power consumption and layout area as compared to conventional digital counters. The analog counter circuit of the present disclosure can also provide much better bias supply management, step accuracy, multi-element step uniformity and lower supply spiking as compared to conventional analog counter architectures. The compact size of the disclosed counter circuit allows better integration of arrayed elements, such as, an array of image sensing pixels or an array of artificial neurons.

In an embodiment, a unit delay circuit comprises a first path configured to delay a first input signal to output a first output signal when a selection signal is inactivated, a second path configured delay a second input signal to output a second output signal when the selection signal is inactivated, and a third path configured to delay the first input signal to output the second output signal when the selection signal is activated.

In an embodiment, a unit delay circuit comprises a first path configured to delay a first input signal to output a first output signal when a selection signal is inactivated, a second path configured delay a second input signal to output a second output signal when the selection signal is inactivated, and a third path configured to delay the first input signal to output the second output signal when the selection signal is activated.

Methods, systems, and apparatuses, including computer programs encoded on computer-readable media, for a microwave cavity resonator stabilized oscillator, are described. The oscillator can include a cavity resonator configured to resonate at least at one predetermined resonant frequency in a GHz frequency range. The oscillator can include circuitry including a microwave amplifier, a low pass filter and a phase shifter. The circuitry may be arranged in a feedback loop configuration, and may be at least partially mounted above a first surface of the cavity resonator. The circuitry may be electrically coupled to the cavity resonator to form an oscillator. The circuitry can include a first delay line segment that is selected instead of at least one other delay line segments for wire-bond connection to complete the feedback loop configuration at zero degree phase.

A system for filter enhancement, preferably including one or more analog taps and a controller, and optionally including one or more couplers. The system is preferably configured to integrate with a filter, such as a passband filter or other frequency-based filter. The system can be configured to integrate with an RF communication system, an RF front end, or any other suitable RF circuitry. A method for filter enhancement, preferably including configuring one or more analog taps, and optionally including calibrating a system for filter enhancement and/or receiving temperature information.