An impedance control circuit includes a configuration channel interface, three resistors and two transistors. The configuration channel interface is coupled to a universal serial bus device. The first resistor has a first terminal coupled to the configuration channel interface. The first transistor has a first terminal coupled to a second terminal of the first resistor, and a second terminal coupled to a system voltage terminal. The second transistor has a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to the system voltage terminal. The second resistor has a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to a control terminal of the second transistor. The third resistor has a first terminal coupled to the second terminal of the second resistor, and a second terminal coupled to the system voltage terminal.

A matching circuit which can handle a plurality of frequencies is provided. The matching circuit includes a transistor and an inductor. The matching circuit uses capacitance formed between a gate and a source/drain (referred to as capacitance Cgsd below) of the transistor as a condenser. The capacitance Cgsd changes with the voltage of the gate with respect to the source (referred to as voltage Vgs below). The transistor included in the matching circuit is an OS transistor including a metal oxide in a channel formation region. The OS transistor features larger variation in capacitance Cgsd with respect to the voltage Vgs than the MOSFET that uses silicon, which enables the matching circuit to handle alternating-current signals in a wide frequency range.

A high frequency circuit includes a transistor having an input electrode that inputs a high frequency signal and an output electrode that outputs the high frequency signal, a transmission line that is connected to any one of the input electrode and the output electrode, and transmits the high frequency signal, a coupling line electrically separated from the transmission line to an extent that an electromagnetic field coupling is enabled with the transmission line, and a resonance circuit that is connected between a first end of the coupling line and a reference potential, and minimizes an impedance between the first end and the reference potential at a resonance frequency.

A high frequency circuit includes a transistor having an input electrode that inputs a high frequency signal and an output electrode that outputs the high frequency signal, a transmission line that is connected to any one of the input electrode and the output electrode, and transmits the high frequency signal, a coupling line electrically separated from the transmission line to an extent that an electromagnetic field coupling is enabled with the transmission line, and a resonance circuit that is connected between a first end of the coupling line and a reference potential, and minimizes an impedance between the first end and the reference potential at a resonance frequency.

An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.

An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.

Technologies for impedance matching networks for qubits are disclosed. In one illustrative embodiment, an impedance matching network matches a 50 Ohm transmission line to a spin qubit with a state-dependent resistance of 100 kiloohms to 105 kiloohms. The illustrative impedance matching network is tunable, allowing the impedance transformation ratio to be changed without significantly changing the matching frequency of the impedance matching network. In some embodiments, the impedance matching network matches a 50 Ohm transmission line to a lower-resistance state of a qubit. In other embodiments, the impedance matching network matches a 50 Ohm transmission line to an impedance value in between a lower-resistance state and a higher-resistance state of a qubit.

Technologies for impedance matching networks for qubits are disclosed. In one illustrative embodiment, an impedance matching network matches a 50 Ohm transmission line to a spin qubit with a state-dependent resistance of 100 kiloohms to 105 kiloohms. The illustrative impedance matching network is tunable, allowing the impedance transformation ratio to be changed without significantly changing the matching frequency of the impedance matching network. In some embodiments, the impedance matching network matches a 50 Ohm transmission line to a lower-resistance state of a qubit. In other embodiments, the impedance matching network matches a 50 Ohm transmission line to an impedance value in between a lower-resistance state and a higher-resistance state of a qubit.

An integrated circuit with self-reference impedance includes an input/output pin provided for connection to an external impedance, a local impedance, a reference power circuit, a switching circuit, and a control circuit. The switching circuit is configured to conduct a connection between the input/output pin and the reference power circuit in a first state and to conduct a connection between the local impedance and the reference power circuit in a second state. The control circuit is configured to detect whether the external impedance is connected to the input/output pin or not and to generate a detection signal. The control circuit controls the switching circuit into the first state or the second state according to the detection signal. In the first state, the reference power circuit generates a reference signal according to the external impedance. In the second state, the reference power circuit generates the reference signal according to the local impedance.

An integrated circuit with self-reference impedance includes an input/output pin provided for connection to an external impedance, a local impedance, a reference power circuit, a switching circuit, and a control circuit. The switching circuit is configured to conduct a connection between the input/output pin and the reference power circuit in a first state and to conduct a connection between the local impedance and the reference power circuit in a second state. The control circuit is configured to detect whether the external impedance is connected to the input/output pin or not and to generate a detection signal. The control circuit controls the switching circuit into the first state or the second state according to the detection signal. In the first state, the reference power circuit generates a reference signal according to the external impedance. In the second state, the reference power circuit generates the reference signal according to the local impedance.