Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

A switch includes an input terminal, an output terminal, and a stack including transistors, such as, for example, field effect transistors, coupled in series, the stack being coupled between the input terminal and the output terminal. The switch also includes at least one switching element configured to be selectively operated in a conducting state or a non-conducting state, and at least one overvoltage protection element coupled to the stack by the at least one switching element. By way of example, the switch can implement a radio-frequency switch.

An apparatus for converting power includes at least one impedance matching network which receives an electrical signal. The apparatus includes at least one AC to DC converter in communication with the impedance matching network. Also disclosed is a method for powering a load and an apparatus for converting power and additional embodiments of an apparatus for converting power.

An apparatus for converting power includes at least one impedance matching network which receives an electrical signal. The apparatus includes at least one AC to DC converter in communication with the impedance matching network. Also disclosed is a method for powering a load and an apparatus for converting power and additional embodiments of an apparatus for converting power.

A multi-mode wireless power receiving device and method are disclosed. The multi-mode wireless power receiving device can comprise: an antenna module comprising an outer loop and an inner loop; a mode control unit for controlling an operation mode of the antenna module; a switch connecting the outer loop and the inner loop, and operated by the mode control unit; an outer loop module for supporting a magnetic resonance method and NFC communication by using the outer loop, according to the operation of the switch; and an inner loop module using the outer loop and the inner loop simultaneously so as to support a magnetic induction method according to the operation of the switch, thereby transmitting power.

A multi-mode wireless power receiving device and method are disclosed. The multi-mode wireless power receiving device can comprise: an antenna module comprising an outer loop and an inner loop; a mode control unit for controlling an operation mode of the antenna module; a switch connecting the outer loop and the inner loop, and operated by the mode control unit; an outer loop module for supporting a magnetic resonance method and NFC communication by using the outer loop, according to the operation of the switch; and an inner loop module using the outer loop and the inner loop simultaneously so as to support a magnetic induction method according to the operation of the switch, thereby transmitting power.

An eVC including coarse and fine tuning networks. The coarse tuning network includes a circuit: receiving a RF input signal from a RF generator; outputting a RF output signal to a reference terminal or load; and receiving a DC bias voltage. The circuit is switched between first and second states. A capacitance of the circuit is based on the DC bias voltage while in the first state and is not based on the DC bias voltage while in the second state. The fine tuning network is connected in parallel with the coarse tuning network and includes a varactor. The varactor includes: a first diode receiving the RF input signal; and a second diode connected in a back-to-back configuration with the first diode and outputting a RF output signal to the reference terminal or load. A capacitance of the varactor is based on a second received DC bias voltage.

An eVC including coarse and fine tuning networks. The coarse tuning network includes a circuit: receiving a RF input signal from a RF generator; outputting a RF output signal to a reference terminal or load; and receiving a DC bias voltage. The circuit is switched between first and second states. A capacitance of the circuit is based on the DC bias voltage while in the first state and is not based on the DC bias voltage while in the second state. The fine tuning network is connected in parallel with the coarse tuning network and includes a varactor. The varactor includes: a first diode receiving the RF input signal; and a second diode connected in a back-to-back configuration with the first diode and outputting a RF output signal to the reference terminal or load. A capacitance of the varactor is based on a second received DC bias voltage.

An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.