A hardware downscaling module and downscaling methods for downscaling a two-dimensional array of values. The hardware downscaling unit comprises a first group of one-dimensional downscalers; and a second group of one-dimensional downscalers; wherein the first group of one-dimensional downscalers is arranged to receive a two-dimensional array of values and to perform downscaling in series in a first dimension; and wherein the second group of one-dimensional downscalers is arranged to receive an output from the first group of one-dimensional downscalers and to perform downscaling in series in a second dimension.

An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater's inputs are connected to phase outputs of the delay line. The gater's clock input is tied to the DLL signal input, and its outputs feed into the PFD inputs. The PFD generates outputs that are used by a loop filter to control the speed of the delay line.

A method and system for the design and implementation of an optimally factored filter is presented. Pairs of angle values are organized in pairing candidates and a threshold is defined to indicate an upper bound on the number of pairing candidates. A first pairing candidate is exchanged above the threshold with a second pairing candidate below the threshold and a matrix is generated based on the pairing candidates below the threshold. A lowest predicted total quantization cost between all pairing candidates represented within the matrix is determined and the pairing candidates that result in the lowest predicted total quantization cost are used to determine the coefficients of the filter.

A method and system for the design and implementation of an optimally factored filter is presented. Pairs of angle values are organized in pairing candidates and a threshold is defined to indicate an upper bound on the number of pairing candidates. A first pairing candidate is exchanged above the threshold with a second pairing candidate below the threshold and a matrix is generated based on the pairing candidates below the threshold. A lowest predicted total quantization cost between all pairing candidates represented within the matrix is determined and the pairing candidates that result in the lowest predicted total quantization cost are used to determine the coefficients of the filter.

A filter system for filtering an input signal comprises a network of Prism filters including at least one cosine Prism filter and at least one sine Prism filter. The network comprises a first branch (210) in parallel with a second branch, (220) each branch arranged to receive the input signal as an input, the first branch comprising the cosine Prism filter/s (211), the second branch comprising the sine Prism filter/s (221). The network of Prism filters is arranged to generate an output signal based on a combination of an output of the first branch with an output of the second branch. A method of designing a convolutional filter is also provided, comprising inputting a test signal into a filter system to generate an impulse response of the filter system and generating a convolutional filter based on the impulse response.

A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.

There are provided a signal generator capable of flexibly increasing the number of taps while realizing high-speed emphasis switching and an emphasis switching method using the signal generator. A signal generator includes: an emphasis addition circuit including at least one finite impulse response (FIR) filter unit that generates an emphasis waveform pattern by adding an emphasis to a pattern of a pulse amplitude modulation (PAM) signal including multi-values which are two or more values; and a tap value setting unit that switches M tap values C(0), C(1), . . . , and C(1M) and sets the M tap values C(0), C(1), . . . , and C(1M) to each FIR filter unit according to an emphasis switching request from a DUT 100. The FIR filter unit is configured on an FPGA or an ASIC.

The present disclosure provides a method for realizing a speaker array-oriented multiple filter system and a related device, belonging to the technical field of audio systems. The method includes: merging, before real-time audio processing, filters of a plurality of sound effect modules in an audio signal processing flow offline to form a finite impulse response (FIR) multiple filter network. The present disclosure places most of computation in an offline processing flow by merging the filters of the plurality of sound effect modules in offline convolution, so that the computation amount of real-time processing is greatly reduced.

An integrated circuit comprising a plurality MAC pipelines wherein each MAC pipeline includes: (i) a plurality of MACs connected in series and (ii) a plurality of data paths including an accumulation data path, wherein each MAC includes a multiplier to multiply to generate product data and an accumulator to generate sum data. The integrated circuit further comprises a plurality of control/configure circuits, wherein each control/configure circuit connects directly to and is associated with a MAC pipeline, wherein each control/configure circuit includes an accumulation data path which is configurable to directly connect to the accumulation data path of the MAC pipeline to form an accumulation ring when the control/configure circuit is configured in an accumulation mode, and an output data path configurable to directly connect to the output of the accumulation data path of the MAC pipeline when the control/configure circuit is configured in an output data mode.

There is provided mechanisms for enabling linearization of a non-linear electronic device. A method is performed by a linearizer device. The method comprises receiving an input signal destined to be input to the non-linear electronic device. Input-output characteristics of the non-linear electronic device is represented by a model. The model is defined by a mathematical expression, and wherein input-output characteristics of the linearizer device is given by the linearization function. The linearization function is determined by applying a function recursion to the mathematical expression of the model. The method comprises obtaining an output signal by subjecting the input signal to the linearization function. The method comprises providing the output signal, instead of the input signal, as input to the non-linear electronic device, thereby enabling linearization of the non-linear electronic device.