A finite impulse response (FIR) filter circuit design method using approximate computing, the FIR filter circuit design method including: replacing adders of the FIR filter with approximate adders; and performing a synthesis work according to a set approximate synthesis flow when the replacing of the adders of the FIR filter are replaced with the approximate adders is performed, wherein, in the approximate synthesis flow, a numeric column of each of the approximate adders is divided into an accurate part and an inaccurate part, and a numeric column of the inaccurate part is approximated. In the FIR filter, conventional adders/subtractors are replaced with addition/subtraction having an automated synthesis flow so that energy consumption can be reduced.

In one embodiment an adaptive filter structure comprises a detector circuit (10) configured to receive an input signal (Sin), to detect a presence of a sweeping interference in the input signal, and upon detection of such sweeping interference to provide a first trigger signal (T1) to a delay circuit (20), wherein the first trigger signal (T1) comprises a first frequency indication (f1); the delay circuit (20) is configured, upon receiving the first trigger signal (T1), to provide a second trigger signal (T2) to a tracker circuit (30) after an adjustable amount of time; the tracker circuit (30) is configured, upon receiving the second trigger signal (T2), to estimate a frequency of the sweeping interference using a second frequency indication (f2), to track the estimated frequency and provide the estimated frequency as a third frequency indication (13) to a notch filter circuit (40); and the notch filter circuit (40) is configured to substantially eliminate the sweeping interference from the input signal (Sin) using the third frequency indication (f3) and therefrom provide an output signal (Sout).

An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater's inputs are connected to phase outputs of the delay line. The gater's clock input is tied to the DLL signal input, and its outputs feed into the PFD inputs. The PFD generates outputs that are used by a loop filter to control the speed of the delay line.

An apparatus and method for performing FIR filtering and blending operations. A processor comprising: a decode unit to decode a packed N-tap finite impulse response (FIR) filter instruction, the packed N-tap FIR filter instruction to indicate one or more source packed data operands comprising a plurality of packed data elements, at least 3 filter coefficients, and a destination storage location, the plurality of packed data elements comprising data from a signal to be filtered and the plurality of filter coefficients specifying a filter function to be applied; and an execution unit comprising an FIR unit coupled with the decode unit, the FIR unit, in response to the packed N-tap FIR filter instruction being decoded by the decode unit, to perform at least N1 multiplications to generate at least N1 products, each of the multiplications comprising one of the filter coefficients multiplied by one of the packed data elements, the execution unit to combine the at least N1 products in accordance with a specified type of FIR filter being implemented to generate a result packed data element to be stored in the destination storage location.

Hybrid analog-digital processing systems are described. An example of a hybrid analog-digital processing system includes photonic accelerator configured to perform matrix-vector multiplication using light. The photonic accelerator exhibits a frequency response having a first bandwidth (e.g., less than 3 GHz). The hybrid analog-digital processing system further includes a plurality of analog-to-digital converters (ADCs) coupled to the photonic accelerator, and a plurality of digital equalizers coupled to the plurality of ADCs, wherein the digital equalizers are configured to set a frequency response of the hybrid analog-digital processing system to a second bandwidth greater than the first bandwidth.

A system comprises a generator control unit (GCU) configured to control a generator. The system includes a first sensor connected to provide feedback to the GCU for generator control. The first sensor is configured to connect to sense at least one of voltage and/or current in a feeder connecting between the generator and a load. The system also includes a second sensor connected to provide feedback to the GCU for generator control. The second sensor is configured to sense at least one of voltage and/or current in a feeder connecting between the generator and the load. The first and second sensors are configured to connect to the feeder apart from one another with feeder impedance therebetween.

The present invention provides a method for equivalent high sampling rate FIR filtering based on FPGA, first, the coefficients h(k) of FIR filter are found by using MATLAB, multiplied by an integer and then rounded for the purpose that the rounded coefficients h(k) can be directly used into a FPGA, then the ADC's output of high data rate f.sub.s is lowered by dividing the ADC's output x(n) into M parallel data streams x.sub.i(n) of low data rate, and the ML samples in one clock circle is obtained by delaying the M parallel data streams x.sub.i(n) simultaneously by 1, 2, . . . , L periods of the synchronous clock, at last, the samples y.sub.i(n) of FIR filtering output is calculated according to the samples selected from the ML samples, and the filtered data y(n) of data rate f.sub.s is obtained by putting the samples y.sub.i(n) together in ascending order of i. Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged.

A detector device for calibrating a digital filter to replicate a transfer function of a signal processing apparatus, comprising: a first input to receive a first signal; a second input configured to receive a response signal of the signal processing apparatus to the first signal; a controllable FIR filter; a comparison-block to compare the phase and amplitude after a correction has been applied by the controllable FIR filter; a feedback loop; and an interpolation-block; wherein the at least one detector is configured to determine, at least, the feedback control signal at a first frequency and at a second frequency, and wherein the interpolation-block is configured to interpolate to determine calibration information for programming of the transfer function of said digital filter.

The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion a compensation circuit and a digital to analog conversion circuit. The compensation circuit includes a filter configured to provide roll off compensation in a baseband frequency using real coefficients. The compensation circuit is configured to convert the first digital signal to a second digital signal so that the second digital signal can be filtered by the filter using the real coefficients.

A method is provided for monitoring a motor within a seat assembly in an automotive vehicle. The method comprises the steps of measuring raw current values drawn by the motor to reposition the seat assembly, temporally dividing the raw current values into sections based on size and variations in the raw current values, filtering the raw current values in each section to obtain filtered current values, detecting local peaks within the filtered current values, and determining a rotational position or a speed of the motor based on the detected local peaks.