Techniques are provided for non-linear filtering of a signal for improved pulse detection and pulse width discrimination. A system implementing the techniques according to an embodiment includes a first linear filter configured to filter an in-phase component of a received signal to a downsample bandwidth and a second linear filter configured to filter a quadrature phase component of the received signal to the downsample bandwidth. The system also includes a magnitude calculation circuit coupled to outputs of the first linear filter and the second linear filter and configured to generate a magnitude signal based on the filtered in-phase component and the filtered quadrature phase component of the received signal. The system further includes a median filter processor coupled to an output of the magnitude calculation circuit and configured to apply a median filter to the magnitude signal to generate a filtered signal having reduced noise while maintaining sharp edge transitions.

Techniques are provided for non-linear filtering of a signal for improved pulse detection and pulse width discrimination. A system implementing the techniques according to an embodiment includes a first linear filter configured to filter an in-phase component of a received signal to a downsample bandwidth and a second linear filter configured to filter a quadrature phase component of the received signal to the downsample bandwidth. The system also includes a magnitude calculation circuit coupled to outputs of the first linear filter and the second linear filter and configured to generate a magnitude signal based on the filtered in-phase component and the filtered quadrature phase component of the received signal. The system further includes a median filter processor coupled to an output of the magnitude calculation circuit and configured to apply a median filter to the magnitude signal to generate a filtered signal having reduced noise while maintaining sharp edge transitions.

A computer-implemented method of performing an operation on an array of values at a processing unit so as to perform a phase of the operation. For each of one or more one-dimensional sequences of values of the array of values a respective section of values of the one-dimensional sequence of values is assigned to each of a plurality of threads, and a first thread of the plurality of threads determines at least one contribution, from the section of values assigned to the first thread, to the phase of the operation that is to be completed by a second thread of the plurality of threads for a neighbouring section of values of the one-dimensional sequence of values. The at least one contribution is written to a memory, and a second thread of the plurality of threads reads the at least one contribution from the memory. and completes the phase of the operation for the neighbouring section of values assigned to the second thread in dependence on the at least one contribution read from the memory in order to generate a section of processed values.

A method for determining a finite impulse response filter, including generation of a plurality of individuals presenting configuration parameters, and cyclic implementation of the following operations in relation to each current population of configuration parameters: evaluation by an objective function of each individual, evaluation by at least one constraint function of each individual, selection of a group of individuals among all the individuals based on their evaluations by the objective function and the constraint function and formation of parent individuals, crossover of parent individuals to form a new population, mutation of individuals in the new population, and verification of a stopping criterion.

An electronic device may include one or more filters arranged to filter an input signal and circuitry that generates a filtered output corresponding to an application of the one or more filters on the input signal. The circuitry may generate the filtered output based on determination of a multiplication factor based on respective coefficients of filter components of the one or more filters, determination of an addition offset based on respective states of the one or more filters, and a combination of the multiplication factor, the addition offset, and the input signal.

A digital filter circuit includes retrieve stream data as a digital signal, and cyclically operate a first phase and a second phase. The circuit includes a short-term storage unit configured to store a local state variable, a long-term storage unit configured to store a global state variable, a first phase synthesizing unit that outputs the digital signal in the first phase under an influence of the local state variable stored in the short-term storage unit, and a second phase synthesizing unit that outputs the digital signal in the second phase under an influence of the global state variable stored in the long-term storage unit, where an output from the first phase synthesizing unit and an output from the second phase synthesizing unit are caused to generate an interference due to a phase shift.