A circuit for correction of a signal which is susceptible to baseline wander. The circuit includes a front-end signal processing circuit, a slicer circuit, and a summing cross-over filter circuit. The front-end signal processing circuit includes a digital processing logic circuit and is used to process an input signal by mitigating signal artifacts. The slicer circuit samples the processed input signal and, therefrom, generates a symbol output derived from the sampled processed input signal. The summing cross-over filter circuit is arranged between the front-end signal processing circuit and the slicer circuit and mitigates baseline wander in the symbol output.

In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.

Techniques to increase a data throughput rate of a filter circuit by preloading selectable memory circuits of the filter circuit with reference data, sampling input data at an input of the filter circuit, combining the sampled input data with the preloaded reference data, and generating a filter output based on the combined sampled input data and preloaded reference data.

Methods and apparatus are provided for adapting gain elements in digital filter chains. In one example, a digital filter chain includes a first digital filter and a second digital filter having an input coupled to an output of the first digital filter. A common gain is applied to signal samples passing between the first digital filter and the second digital filter, the common gain corresponding to a product of an output gain associated with the first digital filter and an input gain associated with the second digital filter. In another example, a digital filter includes an adjustable input gain element and an adjustable output gain element. The adjustable input gain element is configured to apply a gain value to an input signal sample, the gain value comprising a resultant difference of a bitshift configured for the digital filter and a bitwidth extension value. The adjustable output gain element is configured to apply an opposite of the gain value to an output signal sample.

Trans-filter/Detectors are extremely sensitive circuits that recover exponentially modulated signals buried in noise. They can be used wherever Matched Filter/Coherent Detectors are used and operate at negative input signal-to-noise ratios to recover RADAR, SONAR, communications, or data signals, as well as reduce phase noise of precision oscillators. Input signal and noise is split into two paths where complementary derivatives are extracted. Outputs of the two paths are equal in amplitude and 180 degrees relative to each other at the band center frequency. The outputs are summed, causing stationary in-band noise to be reduced by cancellation while exponentially modulated signals are undiminished. Trans-filters are Linear Time Invariant circuits, have no noise x noise threshold and can be cascaded, increasing output signal-to-noise ratio prior to detection. Trans-filters are most sensitive to all types of digital modulation, producing easily detected polarized pulses synchronous with data transitions. Trans-filters do not require coherent conversion oscillators and complex synchronizing circuits.

A sensor circuit is provided with a chopper-stabilized amplifier circuit configured to receive a signal from at least one magnetic sensing element, a sigma-delta modulator (SDM) configured to receive a signal from the chopper-stabilized amplifier circuit, and a feedback circuit configured to reduce ripple in a signal generated by the chopper-stabilized amplifier circuit. The feedback circuit includes a demodulator to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate, a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal, and a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit.

The equalization filter implements an equalization of at least one signal distorted by a measurement setup. The filter coefficients of the equalization filter can be determined by minimizing a cost function K in which only sequences of filter coefficients which exert significant influence on the equalization are taken into consideration.

Droop caused by a filter may be compensated by applying a pre-filter to the audio signal that cancels out, at least in part, the droop caused by the filter. The pre-filter may implement magnitude compensation that causes an approximately flat passband response when the pre-filtered signal is passed through the filter. The pre-filter may be applied to one-bit wide data streams, such as high-fidelity direct stream digital (DSD) audio data or other one-bit wide data such as pulse-density modulation (PDM) encoded data. The pre-filtering and filtering may be implemented in components of an audio processor, such as in a digital-to-analog converter (DAC). The pre-filtering may include upsampling the one-bit wide data to form symbols and substituting an eighth bit of the symbol with an inverted version of an earlier-received bit.

A circuit for correction of a signal which is susceptible to baseline wander. The circuit includes a front-end signal processing circuit, a slicer circuit, and a summing cross-over filter circuit. The front-end signal processing circuit includes a digital processing logic circuit and is used to process an input signal by mitigating signal artifacts. The slicer circuit samples the processed input signal and, therefrom, generates a symbol output derived from the sampled processed input signal. The summing cross-over filter circuit is arranged between the front-end signal processing circuit and the slicer circuit and mitigates baseline wander in the symbol output.

A method and apparatus to compensate for distortion of a waveform due to the skin effect in a current shunt. The method includes modeling the complex impedance of the shunt as component complex impedances. By designing a filter corresponding to the component complex impedances, the distortion of a waveform across the shunt may be reversed to provide an accurate replica of the undistorted waveform.