Prism signal processing is a new FIR filtering technique that can offer a fully recursive calculation and elegant filter design. Its low design and computational cost may be particularly suited to the autonomous signal processing requirements for the Internet of Things. Arbitrarily narrow band-pass filters may be designed and implemented using a chain of Prisms and a simple yet powerful procedure. Using the described method and system, an ultra-narrowband filter can be evaluated in fractions of a microsecond per sample on a desktop computer. To achieve this update rate using a conventional non-recursive FIR calculation would require supercomputer resources. FPGA embodiments of the system demonstrate computation efficiency and broad applications of the technique.

Techniques are provided for a dynamically reconfigurable two times (2) oversampled channelizer. A channelizer implementing the techniques according to an embodiment includes a polyphase filter, a two phase reorder circuit, a fast Fourier transform (FFT) circuit, and a two phase merge circuit. The polyphase filter is configured to filter time domain input data to control spectral shaping of frequency bins of the channelizer output. The two phase reorder circuit is configured to split a 2 oversampled data stream into two parallel, critically sampled data streams. The FFT circuit is configured to transform each stream into the frequency domain. The two phase merge circuit is configured to merge the two streams of frequency domain data into a single stream of 2 oversampled frequency domain data for distribution onto frames of frequency bins. Reconfigurable parameters for the channelizer include filter coefficients, number of filter folds, and number of frequency bins.

A signal processing arrangement generates electrical stimulation signals to electrode contacts in an implanted cochlear implant array. An input sound signal is processed to generate band pass signals that each represent an associated band of audio frequencies. A spectrogram representative of frequency spectrum present in the input sound signal is generated. A characteristic envelope signal is produced for each band pass signal based on its amplitude. An active contour model is applied to estimate dominant frequencies present in the spectrogram, and the estimate is used to generate stimulation timing signals for the input sound signal. The electrode stimulation signals are produced for each electrode contact based on the envelope signals and the stimulation timing signals.

A Scalable Finite Impulse Response (SFIR) filter includes a pre-processing section, a post-processing section, and a finite impulse response (FIR) Matrix. The FIR Matrix is coupled to the pre-processing section and the post-processing section. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths. Each filter tap of the plurality of filter taps has at least a first input, a second input, a multiplexer coupled to the first input and the second input, and a first flip-flop coupled to an output of the multiplexer. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap of the plurality of filter taps.

To collect highly accurately filter-processed data. Sensor signals are acquired from sensors in predetermined data acquisition periods, a filtering process is performed on the sensor signals, time series data generated by extracting some of the filtered sensor signals is transmitted to an external device in a predetermined data transmission period that is longer than the data acquisition period, and the data transmission period is synchronized with a communication period of the external device.

A filter circuit includes multiple registers, a switch circuit, multiple multipliers and a summation circuit. Each register is configured to store an input. The switch circuit is coupled to the registers and configured to receive the inputs from the registers as a series of registered inputs and adjust arrangement of the inputs of the series of registered inputs to generate a series of rearranged inputs according to a count value. The count value is accumulated in response to reception of a new input of the filter circuit. The multipliers are coupled to the switch circuit. The inputs of the series of rearranged inputs are sequentially provided to the multipliers. Each multiplier is configured to generate a multiplication result according to the received input and a coefficient. The summation circuit is coupled to the multipliers and configured to sum up the multiplication results to generate an output.

A Scalable Finite Impulse Response (SFIR) filter is disclosed. The SFIR filter includes a pre-processing section, a post-processing section, and a finite impulse response (FIR) Matrix. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths in signal communication with each filter tap. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap and the pre-processing section and post-processing section are in signal communication with the FIR Matrix.

A radio communication receiver and a method performed by the radio communication receiver for configuring a Notch filter of the radio communication receiver. The method comprises retrieving stored and previously determined filter coefficients from a set of filter coefficients, where the retrieved filter coefficients constitute a fraction of the total number of filter coefficients; and setting the rest of the filter coefficients to one. The method further comprises normalising the retrieved filter coefficients; and transforming the filter coefficients such that the Notch position ends up at the one or more frequencies to be filtered out.

A Scalable Finite Impulse Response (SFIR) filter includes a pre-processing section, a post-processing section, and a finite impulse response (FIR) Matrix. The FIR Matrix is coupled to the pre-processing section and the post-processing section. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths. Each filter tap of the plurality of filter taps has at least a first input, a second input, a multiplexer coupled to the first input and the second input, and a first flip-flop coupled to an output of the multiplexer. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap of the plurality of filter taps.

A Scalable Finite Impulse Response (SFIR) filter is disclosed. The SFIR filter includes a pre-processing section, a post-processing section, and a finite impulse response (FIR) Matrix. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths in signal communication with each filter tap. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap and the pre-processing section and post-processing section are in signal communication with the FIR Matrix.