A finite impulse response (FIR) filter circuit design method using approximate computing, the FIR filter circuit design method including: replacing adders of the FIR filter with approximate adders; and performing a synthesis work according to a set approximate synthesis flow when the replacing of the adders of the FIR filter are replaced with the approximate adders is performed, wherein, in the approximate synthesis flow, a numeric column of each of the approximate adders is divided into an accurate part and an inaccurate part, and a numeric column of the inaccurate part is approximated. In the FIR filter, conventional adders/subtractors are replaced with addition/subtraction having an automated synthesis flow so that energy consumption can be reduced.

The present disclosure describes methods, systems, and computer program products for a reducing crest factors. An input signal is received. The input signal includes a clipping signal that reduces a peak amplitude of a source signal based on a predetermined clipping level. The input signal is transposed to a plurality of transposed signals using a plurality of multipliers. A feedback signal is generated based on the plurality of transposed signals using a first plurality of delay taps. A windowing signal is generated based on the feedback signal. The windowing signal is used to reduce a crest factor of the source signal.

Systems, apparatuses, and methods for implementing a low power filter. A low power filter may generate a reference sum from a reference vector in order to reduce the number of additions which are needed to filter an input sample vector. The reference sum may be used as the starting point for filtering the input sample vector. Then, each input sample of the input sample vector may be compared to a corresponding reference vector sample. If an input sample is different from the corresponding reference vector sample, a correction value based on the corresponding filter coefficient value may be added or subtracted from the reference sum. After all input samples have been compared to corresponding reference vector values and all correction values applied to the reference sum, the modified reference sum may be the output of the filter.

A system and method for symmetrical filtering of an input string may include loading, into at least one vector register, in a single read cycle, a subset of right-side data elements and a subset of left-side data elements of the input string. The input string may be stored sequentially in a memory unit. The right-side data elements and the left-side data elements may be equally distant from the center of the input string and may be separated by a whole number of rows in the memory. The system and method may include performing filtering of the input string using a symmetrical filter with the loaded right-side data elements and left-side data elements.

An apparatus for parallel filtering, including a multi-granularity memory, a data cache device, a coefficient buffer broadcast device, a vector operation device and a command queue device. The multi-granularity memory is configured to store data to be filtered, filter coefficients and filtering result data. The data cache device is configured to cache, read and update the data to be filtered. The coefficient buffer broadcast device is configured to cache and broadcast the read filter coefficients. The command queue device is configured to store and output a queue of operation commands for the parallel filtering operation. The vector operation device is configured to perform a vector operation based on the data to be filtered and the output coefficient data, and write an operation result into the multi-granularity filtering result storage unit. A method is also provided. The apparatus and method have a fast filtering speed, a smaller number of accesses, an improved usage efficiency, a reduced power consumption and a wide application scope.

A filter system for filtering an input signal comprises a network of Prism filters including at least one cosine Prism filter and at least one sine Prism filter. The network comprises a first branch (210) in parallel with a second branch, (220) each branch arranged to receive the input signal as an input, the first branch comprising the cosine Prism filter/s (211), the second branch comprising the sine Prism filter/s (221). The network of Prism filters is arranged to generate an output signal based on a combination of an output of the first branch with an output of the second branch. A method of designing a convolutional filter is also provided, comprising inputting a test signal into a filter system to generate an impulse response of the filter system and generating a convolutional filter based on the impulse response.

A configurable generic filter hardware block and corresponding methods are provided. A configurable generic filter hardware block includes a plurality of multipliers; a plurality of adders; and one or more multiplexers. The, configurable generic filter hardware block is configured using a header data structure, and the header data structure includes a pointer to a memory location storing a plurality of input samples, a pointer to a memory location storing a plurality of output samples and a coefficient selection control value. The configurable generic filter hardware block is optionally invoked by a convolution instruction in one or more of a vector processor and a state machine. An exemplary Generic Filter Iteration loads input samples; selects coefficients; convolves the input samples and the selected coefficients and stores output samples. The header data structures are optionally stored sequentially in memory and processed in a single loop.

According to one aspect of the invention, there is provided a method of operating a finite impulse response filter comprising an input; an output; and a plurality of storage elements, each coupled to the input via a sample switch and to the output via a transfer switch, the method comprising: during charging of the plurality of storage elements, applying a sample clock signal to each of the sample switches that achieves an operation mode where up to every one of the sample switches is simultaneously closed to connect all of the plurality of storage elements to the input; and during averaging of the plurality of storage elements, applying a transfer clock signal to each of the transfer switches to close one or more of the transfer switches to connect the storage elements, having charge stored therein, to the output.

The present disclosure describes methods, systems, and computer program products for a reducing crest factors. An input signal is received. The input signal includes a clipping signal that reduces a peak amplitude of a source signal based on a predetermined clipping level. The input signal is transposed to a plurality of transposed signals using a plurality of multipliers. A feedback signal is generated based on the plurality of transposed signals using a first plurality of delay taps. A windowing signal is generated based on the feedback signal. The windowing signal is used to reduce a crest factor of the source signal.