Prism signal processing is a new FIR filtering technique that can offer a fully recursive calculation and elegant filter design. Its low design and computational cost may be particularly suited to the autonomous signal processing requirements for the Internet of Things. Arbitrarily narrow band-pass filters may be designed and implemented using a chain of Prisms and a simple yet powerful procedure. Using the described method and system, an ultra-narrowband filter can be evaluated in fractions of a microsecond per sample on a desktop computer. To achieve this update rate using a conventional non-recursive FIR calculation would require supercomputer resources. FPGA embodiments of the system demonstrate computation efficiency and broad applications of the technique.

A filter is disclosed. The filter includes at least one first multiplication approximation unit, for approximating at least one first multiplication operation corresponding to at least one first coefficient with at least one first bit-wise shift operation; and at least one second multiplication approximation unit, for approximating at least one second multiplication operation corresponding to at least one second coefficient with a plurality of second bit-wise shift operations and at least one addition operation.

A filter is disclosed. The filter includes at least one first multiplication approximation unit, for approximating at least one first multiplication operation corresponding to at least one first coefficient with at least one first bit-wise shift operation; and at least one second multiplication approximation unit, for approximating at least one second multiplication operation corresponding to at least one second coefficient with a plurality of second bit-wise shift operations and at least one addition operation.

An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

The present invention relates to a method and an apparatus for processing a signal, which are used for effectively reproducing a multimedia signal, and more particularly, to a method and an apparatus for processing a signal, which are used for implementing filtering for multimedia signal having a plurality of subbands with a low calculation amount.

To this end, provided are a method for processing a multimedia signal including: receiving a multimedia signal having a plurality of subbands; receiving at least one proto-type filter coefficients for filtering each subband signal of the multimedia signal; converting the proto-type filter coefficients into a plurality of subband filter coefficients; truncating each subband filter coefficients based on filter order information obtained by at least partially using characteristic information extracted from the corresponding subband filter coefficients, the length of at least one truncated subband filter coefficients being different from the length of truncated subband filter coefficients of another subband; and filtering the multimedia signal by using the truncated subband filter coefficients corresponding to each subband signal and an apparatus for processing a multimedia signal using the same.

Prism signal processing is a new FIR filtering technique that can offer a fully recursive calculation and elegant filter design. Its low design and computational cost may be particularly suited to the autonomous signal processing requirements for the Internet of Things. Arbitrarily narrow band-pass filters may be designed and implemented using a chain of Prisms and a simple yet powerful procedure. Using the described method and system, an ultra-narrowband filter can be evaluated in fractions of a microsecond per sample on a desktop computer. To achieve this update rate using a conventional non-recursive FIR calculation would require supercomputer resources. FPGA embodiments of the system demonstrate computation efficiency and broad applications of the technique.

The present application discloses a filtering method and a filtering device of a filter, a filter and a storage medium. The method includes: obtaining a clock input signal and a clock output signal and comparing them, and determining a phase relationship between the clock input signal and the clock output signal according to a comparison result; determining a decimal deviation factor according to the phase relationship in determining that the phase relationship meets a preset condition; and filtering a sample input signal according to the decimal deviation factor to obtain a filtered sample output signal. The present application can obtain an accurate decimal deviation factor, by obtaining the phase relationship between the clock input signal and the clock output signal, in determining that the phase relationship meets a preset condition, and can adjust the sample input signal according to the decimal deviation factor to obtain a smooth sample output signal.

A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.

A method includes receiving an input digital signal and applying the input digital signal to digital filter processing with a corner frequency to produce a filtered output digital signal. The digital filter processing includes a set of multiplication operations using a set of filter multiplication coefficients. The set of multiplication operations is performed by alternately using a first set of approximate multiplication coefficients and a second set of approximate multiplication coefficients different from the first set of approximate multiplication coefficients. The approximate multiplication coefficients in the first set of approximate multiplication coefficients and the second set of approximate multiplication coefficients approximate multiplication coefficients in the set of filter multiplication coefficients as a function of negative power-of-two values. The alternating of multiplication operations results in digital filter processing with average corner frequency approximating the corner frequency.

A clamp logic circuit has a logic circuit, a control terminal, a current clamp circuit and an output terminal. The logic circuit has at least a junction field-effect transistor (JFET). The control terminal receives an input signal. The current clamp circuit has a transistor and a resistor. A first end of the transistor is coupled to the control terminal, a second end of the transistor is coupled to a first end of the resistor, a control end of the transistor is coupled to a reference voltage, and a second end of the resistor is coupled to an input end of the logic circuit. The output terminal is coupled to an output end of the logic circuit.