Patent classifications
H03H17/0248
Clamp logic circuit
A clamp logic circuit has a logic circuit, a control terminal, a current clamp circuit and an output terminal. The logic circuit has at least a junction field-effect transistor (JFET). The control terminal receives an input signal. The current clamp circuit has a transistor and a resistor. A first end of the transistor is coupled to the control terminal, a second end of the transistor is coupled to a first end of the resistor, a control end of the transistor is coupled to a reference voltage, and a second end of the resistor is coupled to an input end of the logic circuit. The output terminal is coupled to an output end of the logic circuit.
Fractional scaling digital signal processing
A digital signal synthesizer for generating a frequency and/or phase modified digital signal output comprises an input buffer, a transform module, a processing module, and an output buffer. The input buffer receives a digital input that is represented in a frequency domain representation. The transform module stores a fractional order control system that models a desired frequency and/or phase response defined by an assembly of at least one filter component. Each filter component is defined by a Laplace function that is modified to include a non-integer control order having a variable fractional scaling exponent. The processing module multiplies or divides the digital input with the fractional order control system stored in the transform module. Moreover, the output buffer stores a synthesized output of the input, which is modified in the frequency domain, the phase domain, or both according to the desired frequency and/or phase response by the processing module.
Signal output device
A signal output device is provided in a communication apparatus. The communication apparatus communicates with a different one of the communication apparatus using a single line. The signal output device includes a signal output unit. The signal output unit includes a first filter and a second filter. The first filter is provided by a Bessel filter. The second filter is provided by a Chebyshev filter or a Butterworth filter. The signal output unit outputs a signal which is obtained by passing a predetermined signal through the first filter and the second filter. The signal output from the signal output unit has a pass characteristic of the first filter and a pass characteristic of the second filter. A cutoff frequency of the first filter is set to be lower than a cutoff frequency of the second filter.
SIGNAL OUTPUT DEVICE
A signal output device is provided in a communication apparatus. The communication apparatus communicates with a different one of the communication apparatus using a single line. The signal output device includes a signal output unit. The signal output unit includes a first filter and a second filter. The first filter is provided by a Bessel filter. The second filter is provided by a Chebyshev filter or a Butterworth filter. The signal output unit outputs a signal which is obtained by passing a predetermined signal through the first filter and the second filter. The signal output from the signal output unit has a pass characteristic of the first filter and a pass characteristic of the second filter. A cutoff frequency of the first filter is set to be lower than a cutoff frequency of the second filter.
Multi-Channel Scalable EEG Acquisition System on a Chip with Integrated Patient Specific Seizure Classification and Recording Processor
An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.
Analog-to-digital converter and control method thereof
The present disclosure relates to an analog-to-digital converter (ADC) and a method for controlling an ADC. The ADC includes a plurality of quantization levels for analog-to-digital conversion. The ADC is adapted for utilizing a subset of the plurality of quantization levels for analog-to-digital signal conversion. The subset is formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level. The method includes using a subset of the plurality of quantization levels for analog-to-digital signal conversion, the subset being formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level.
Delay line
A delay line is constructed by combining a phase generator and a fabric. The phase generator splits a digital input signal in multiple incrementally delayed versions, which are input to the fabric. The fabric has an array of node filters. Inputs of filters in the first array column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form a filter output signal. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other array rows. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements.
METHOD AND DEVICE FOR AUDIO SIGNAL PROCESSING
The present invention relates to a method and an apparatus for processing a signal, which are used for effectively reproducing an audio signal, and more particularly, to a method and an apparatus for processing a signal, which are used for implementing binaural rendering for reproducing multi-channel or multi-object audio signals in stereo with a low calculation amount.
To this end, provided are a method for processing an audio signal including: receiving multi-audio signals including multi-channel or multi-object signals, each of the multi-audio signals including a plurality of subband signals, and the plurality of subband signals including a signal of a first subband group having low frequencies and a signal of a second subband group having high frequencies based on a predetermined frequency band; receiving at least one parameter corresponding to each subband signal of the second subband group, the at least one parameter being extracted from binaural room impulse response (BRIR) subband filter coefficients corresponding to each subband signal of the second subband group; and performing tap-delay line filtering of the subband signal of the second subband group by using the received parameter and an apparatus for processing an audio signal using the same.
Analog-to-digital converter with noise shaping
An analog-to-digital converter (ADC) using an amplifier-based noise shaping circuit. The amplifier-based noise shaping circuit generates a noise shaping signal. A comparator of the ADC has a first input terminal coupled to an output terminal of a capacitive data acquisition converter that captures an analog input, a second input terminal receiving the noise shaping signal, and an output terminal for observation of the digital representation of the analog input. The amplifier-based noise shaping circuit uses an amplifier to amplify a residual voltage obtained from the capacitive data acquisition converter and provides a switched capacitor network between the amplifier and the comparator for sampling the amplified residual voltage and generating the noise shaping signal.
METHOD AND SYSTEM FOR SIGNAL DECOMPOSITION, ANALYSIS AND RECONSTRUCTION
A system and method for representing quasi-periodic waveforms, for example, representing a plurality of limited decompositions of the quasi-periodic waveform. Each decomposition includes a first and second amplitude value and at least one time value. In some embodiments, each of the decompositions is phase adjusted such that the arithmetic sum of the plurality of limited decompositions reconstructs the quasi-periodic waveform. Data-structure attributes are created and used to reconstruct the quasi-periodic waveform. Features of the quasi-periodic wave are tracked using pattern-recognition techniques. The fundamental rate of the signal (e.g., heartbeat) can vary widely, for example by a factor of 2-3 or more from the lowest to highest frequency. To get quarter-phase representations of a component (e.g., lowest frequency rate component) that varies over time (by a factor of two to three) many overlapping filters use bandpass and overlap parameters that allow tracking the component's frequency version on changing quarter-phase basis.