Systems, methods, and computer program product embodiments are disclosed for performing electrophysiology (EP) signal processing. An embodiment includes an electrocardiogram (ECG) circuit board configured to process an ECG signal. The embodiment further includes a plurality of intracardiac (IC) circuit boards, each configured to process a corresponding IC signal. The ECG circuit board and the plurality of IC circuit boards share substantially a same circuit configuration and components. The ECG circuit board further processes the ECG signal using substantially a same path as each IC circuit board uses to process its corresponding IC signal.

A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective signal value over the delay line, and is associated with a respective coefficient. Any given one of the arithmetic units is configured to receive a respective control word. The respective control word specifying: (i) a plurality of trivial multiplication operations, and (ii) a plurality of bit shift operations. Any given one of the arithmetic units is further configured to estimate or calculate a product of the respective signal of the arithmetic unit respective signal value and the respective coefficient of the arithmetic unit by performing the trivial multiplication operations and bit shift operations that are specified by the respective control word that is received at the given arithmetic unit.

In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.

Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

An isolation amplification circuit having an input stage circuitry and a control circuitry stage interconnected through a galvanic isolation barrier. The input stage circuitry includes a first filter network and a second filter network for supplying first and second output signals in response to the application of first and second electrical input signals. The input stage circuitry includes a first feedback path configured for applying a first feedback signal to a common node of the first filter network to close a first feedback loop around the first filter network and a second feedback path configured for applying a second feedback signal to a common node of the second filter network to close a second feedback loop around the second filter network.

A signal processing system is described. The signal processing system includes at least one signal processing path and a control module. The at least one signal processing path includes at least one signal input and at least two filter units. The at least two filter units include at least one hardware filter unit. The at least one signal input is connectable to at least one external electronic component. The control module is connected to the signal input and to the at least two hardware filter units. The control module is configured to determine a frequency response deviation being associated with the at least one external electronic component. The control module further is configured to reconfigure the at least one hardware filter unit such that the frequency response deviation is compensated at least partially. Further, a signal processing method for adapting filter coefficients of a signal processing system is described.