A Finite Impulse Response (FIR) filter is configured to minimize delay and maximize passband power by adjusting the filter coefficients applied to the sampled values. The FIR filter obtains an input signal and samples the input signal to generate a set of sampled input values. The FIR filter generates a set of filter coefficients, with each filter coefficient based on a corresponding sampled input value in the set of sample input values. The FIR filter selects a subset of sampled input values that have been most recently sampled from the input signal, and selects a subset of filter coefficients corresponding to sampled input values that are not the most recently sampled. The subset of sampled input values is combined with the subset of filter coefficients to generate an output value for the FIR filter.

A method is provided that includes performing, by a processor in response to a dual issue multiply instruction, multiplication of operands of the dual issue multiply instruction using multiplication units comprised in a data path of the processor and configured to operate together to determine a product of the operands, and storing, by the processor, the product in a storage location indicated by the dual issue multiply instruction.

A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an mn matrix (A matrix) and a np matrix (B matrix) to generate elements of an mp matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

A 1st frequency reduction circuit of a filter of the invention downsamples the sampling rate of a signal source to a predetermined value to obtain a 1st PCM stream, a 1st frequency raising circuit raises the sampling rate of the 1st PCM stream to be the same as that of the signal source, a 1st delay circuit delays a stream of the signal source, such that its phase is the same as that of the 1st PCM stream, a 1st adder subtracts the frequency raised 1st PCM steam from the delayed stream of the signal source to obtain a passband 1, a j-th frequency reduction circuit downsamples the sampling rate of a (j1)-th PCM stream to a predetermined value to obtain a j-th PCM stream, wherein 2jn, a j-th frequency raising circuit raises the sampling rate of the j-th PCM stream to be the same as that of the (j1)-th PCM stream, a j-th delay circuit delays the (j1)-th PCM stream, such that its phase is the same as that of the j-th PCM stream, a j-th adder subtracts the frequency raised j-th PCM stream from the delayed (j1)-th PCM stream to obtain a passband j, and when j=n, the j-th PCM stream is a passband n+1.

Method and apparatus for nonlinear signal processing include mitigation of outlier noise in the process of analog-to-digital conversion and adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. Methods, processes and apparatus for real-time measuring and analysis of variables include statistical analysis and generic measurement systems and processes which are not specially adapted for any specific variables, or to one particular environment. Methods and corresponding apparatus for mitigation of electromagnetic interference, for improving properties of electronic devices, and for improving and/or enabling coexistence of a plurality of electronic devices include post-processing analysis of measured variables and post-processing statistical analysis. Methods, processes and apparatus for secure communications include low-power communications and physical-layer steganography.

A circuit device includes a digital signal processor (DSP) that performs first up-sampling processing of up-sampling up-sampling target data having a first sampling frequency from the first sampling frequency to a second sampling frequency by first interpolation processing, and an arithmetic circuit that performs second up-sampling processing of up-sampling data output from the DSP from the second sampling frequency to a third sampling frequency by second interpolation processing.