This application presents a direct data recovery from subspaces or parameters subranges of a received OFDM signal preidentified as corresponding to specific data symbols, by applying adaptive inverse signal transformation (AIST) method for reversing both original data coding and deterministic and random distortions introduced by a transmission channel, wherein both reversals are achieved by the same conversion of the subspaces or parameter subranges into data transmitted originally in order to eliminate an intermediate recovery of signals or parameters transmitted originally within the received OFDM signal. The AIST includes using both amplitudes and gradients of amplitudes of OFDM tone signals.

This application presents a direct data recovery from subspaces or parameters subranges of a received OFDM signal preidentified as corresponding to specific data symbols, by applying adaptive inverse signal transformation (AIST) method for reversing both original data coding and deterministic and random distortions introduced by a transmission channel, wherein both reversals are achieved by the same conversion of the subspaces or parameter subranges into data transmitted originally in order to eliminate an intermediate recovery of signals or parameters transmitted originally within the received OFDM signal. The AIST includes using both amplitudes and gradients of amplitudes of OFDM tone signals.

Biquad stage systems and methods include receiving at biquad sections a signal sample, generating, by each biquad section, a pair of output values based on the signal sample, including a first value based on fixed-point processing path and a second value emulating a floating-point processing path, and accumulating the pair of output values from each of the plurality of biquad sections to generate an output signal. The biquad stage receives an N-bit input signal, which is processed by a biquad section. Delay elements delay the signal sample before input to other biquad sections. The delayed signal sample is input to the first processing path and the second processing path of a corresponding biquad stage. By performing the processing based on two paths, a more accurate result can be found when using a reduced word length in the multiply operations resulting in a lowering of the power consumption.

The exemplary embodiments provide a parallel implementation of filters with recursive transfer functions. This can enable a filter to act as a frame filter that may process a frame of multiple samples of data in parallel rather than being limited to processing a single sample of data at a time. Each frame contains plural input samples of data values. The input samples are from a common source and have a time dependency. The exemplary embodiments are suitable for implementing various types of filters in parallel, such as cascaded integrator comb filters, biquad filters and other types of infinite impulse response (IIR) filters. The exemplary embodiments may use polyphase decomposition to decompose a filter with a recursive transfer function into multiple polyphase component filters. The polyphase component filters may be applied to respective samples of data in a parallel pipelined configuration to produce filtered output for the samples of data in parallel.

The exemplary embodiments provide a parallel implementation of filters with recursive transfer functions. This can enable a filter to act as a frame filter that may process a frame of multiple samples of data in parallel rather than being limited to processing a single sample of data at a time. Each frame contains plural input samples of data values. The input samples are from a common source and have a time dependency. The exemplary embodiments are suitable for implementing various types of filters in parallel, such as cascaded integrator comb filters, biquad filters and other types of infinite impulse response (IIR) filters. The exemplary embodiments may use polyphase decomposition to decompose a filter with a recursive transfer function into multiple polyphase component filters. The polyphase component filters may be applied to respective samples of data in a parallel pipelined configuration to produce filtered output for the samples of data in parallel.

An audio signal processor includes a digital filter block configured to receive an audio signal and output a first filtered audio signal, and a phase linearization block configured to receive the first filtered audio signal and output a second filtered audio signal with a more linear phase.

As one example, a filter apparatus includes an input to receive an electrical input signal. The filter apparatus includes a forward path connected between the input and an output of the filter apparatus. A feedback path is connected to provide feedback to the forward path based on an output signal at the output of the filter apparatus. A filter bypass is configured to provide the input signal directly to the output and to the feedback path for an activation phase of the filter apparatus. Diagnostics may also be performed.

As one example, a filter apparatus includes an input to receive an electrical input signal. The filter apparatus includes a forward path connected between the input and an output of the filter apparatus. A feedback path is connected to provide feedback to the forward path based on an output signal at the output of the filter apparatus. A filter bypass is configured to provide the input signal directly to the output and to the feedback path for an activation phase of the filter apparatus. Diagnostics may also be performed.

A digital filter structure and related method of digital filtering are presented. The digital filter structure is arranged to receive one or more clocked input signals having a first clock rate, and which is driven at a second clock rate higher than said first clock rate. The digital filter structure has a plurality of delay elements and multiplexing circuitry arranged to selectively engage the delay elements such that, at every clock cycle of the digital filter structure, a filter operation is performed on a different stream of data. The disclosure can be applied in many different contexts. One particular implementation example is that of an adaptive noise cancellation (ANC) system using sigma-delta infinite impulse response filters. In this context the present disclosure minimizes latency and hardware implementation area by requiring only one filtering circuit for multiple channels of data to be filtered.

A filter assembly, for example for a control loop for controlling the position of at least one element, comprises first and second filters. The first filter suppresses an undesired component in a signal to be filtered. The first filter produces a first signal delay in a first frequency range. The second filter produces a second signal delay in the first frequency range. The second signal delay at least partly compensates the first signal delay.