H03H17/06

FILTER CONTROL METHOD AND FILTER CONTROL DEVICE
20230008531 · 2023-01-12 ·

A filter control method controls a filter that controls frequency characteristics of a sound signal over a plurality of bands. The filter control method is implemented by a computer. The filter control method includes accepting a specifying operation from a user to specify a latency of the filter as a desired latency of the filter, accepting a setting operation from the user to set desired values of two or more parameters, which include phase characteristics and gain, for a respective band among the plurality of bands within a limit range determined based on the desired latency, and generating coefficients for the filter based on the desired values of the two or more parameters for the respective band.

Analog to digital conversion circuit including a digital decimation filtering circuit

An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency. The analog signal includes a set of pure tone components. The first digital signal includes n 1-bit channels. The analog to digital conversion circuit further includes a digital decimation filtering circuit including n anti-aliasing filters operable to sample and filter the n 1-bit channels of the first digital signal to produce n second digital signals and n decimator circuits operable to decimate the n second digital signals to produce n third digital signals at a second data rate frequency. The analog to digital conversion circuit further includes a multiplexor operable to output the n third digital signals at the second data rate frequency on a single bus.

Subcarrier based adaptive equalization of electrical filtering effects on sub-carrier multiplexed signals
11539447 · 2022-12-27 · ·

Consistent with the present disclosure, the above-described subcarrier noise, which may be characterized as a linear filtering effect, may be reduced or eliminated by providing a first multiple-input multiple output (MIMO) circuits at the transmit end of an optical link and providing a second MIMO circuit at the receive end of the optical link. The first MIMO may include a first plurality of filters, each of which may include a finite-impulse response (FIR) filter having variable coefficients or tap weights that may be changed or adapted to minimize subcarrier noise associated with the modulator, as well as D/A and analog circuitry, at the transmit end of the optical link. In addition, the second MIMO may include a second plurality of filters, each of which may also include an FIR filter having variable coefficients or tap weights that may be changed or adapted to minimized subcarrier noise associated with the optical hybrids, as well as A/D and analog circuitry, at the receive end of the optical link. In one example, a least means square (LMS) technique may be employed to calculate desired coefficients or tap weights whereby an error determined based on the signal detected at the receiver is minimized to update the coefficients of the FIR filters.

Subcarrier based adaptive equalization of electrical filtering effects on sub-carrier multiplexed signals
11539447 · 2022-12-27 · ·

Consistent with the present disclosure, the above-described subcarrier noise, which may be characterized as a linear filtering effect, may be reduced or eliminated by providing a first multiple-input multiple output (MIMO) circuits at the transmit end of an optical link and providing a second MIMO circuit at the receive end of the optical link. The first MIMO may include a first plurality of filters, each of which may include a finite-impulse response (FIR) filter having variable coefficients or tap weights that may be changed or adapted to minimize subcarrier noise associated with the modulator, as well as D/A and analog circuitry, at the transmit end of the optical link. In addition, the second MIMO may include a second plurality of filters, each of which may also include an FIR filter having variable coefficients or tap weights that may be changed or adapted to minimized subcarrier noise associated with the optical hybrids, as well as A/D and analog circuitry, at the receive end of the optical link. In one example, a least means square (LMS) technique may be employed to calculate desired coefficients or tap weights whereby an error determined based on the signal detected at the receiver is minimized to update the coefficients of the FIR filters.

Enhanced discrete-time feedforward equalizer

An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N−1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

Enhanced discrete-time feedforward equalizer

An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N−1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

FINITE IMPULSE RESPONSE FILTER
20220399878 · 2022-12-15 · ·

A system, a non-transitory computer readable media and a method for FIR filtering. The method may include obtaining a set of input samples; and concurrently applying a FIR filtering process on the set of input samples to provide a set of FIR filtered output samples. The latter may include calculating intermediate results that represent a first number of coefficient-input sample products, while calculating only some of the first number of coefficient-input sample products, wherein the calculating of the intermediate results is executed by using less than a first number of multipliers.

FINITE IMPULSE RESPONSE FILTER
20220399878 · 2022-12-15 · ·

A system, a non-transitory computer readable media and a method for FIR filtering. The method may include obtaining a set of input samples; and concurrently applying a FIR filtering process on the set of input samples to provide a set of FIR filtered output samples. The latter may include calculating intermediate results that represent a first number of coefficient-input sample products, while calculating only some of the first number of coefficient-input sample products, wherein the calculating of the intermediate results is executed by using less than a first number of multipliers.

Systems and method for a low power correlator architecture using distributed arithmetic
11528013 · 2022-12-13 · ·

Provided herein is an implementation of a finite impulse response (FIR) filter that uses a distributed arithmetic architecture. In one or more example, a data sample with multiple bits is processed through a plurality of bit-level multiply and accumulate circuits, wherein each bit of the data sample corresponds to a bit of the data sample. The output of each bit-level multiply and accumulate circuit can then be shifted by an appropriate amount based on the bit placement of the bit of the data sample that corresponds to the bit-level multiply and accumulate circuit. After each output is shifted by the appropriate amount, the outputs can be aggregated to form a final FIR filter result.

Systems and method for a low power correlator architecture using distributed arithmetic
11528013 · 2022-12-13 · ·

Provided herein is an implementation of a finite impulse response (FIR) filter that uses a distributed arithmetic architecture. In one or more example, a data sample with multiple bits is processed through a plurality of bit-level multiply and accumulate circuits, wherein each bit of the data sample corresponds to a bit of the data sample. The output of each bit-level multiply and accumulate circuit can then be shifted by an appropriate amount based on the bit placement of the bit of the data sample that corresponds to the bit-level multiply and accumulate circuit. After each output is shifted by the appropriate amount, the outputs can be aggregated to form a final FIR filter result.