A method includes converting, by n analog to digital converter circuits, n analog signals into n first digital signals having a first data rate frequency; converting, by n digital decimation filtering circuits, the n first digital signals into n second digital signals having a second data rate frequency; and converting, by n digital bandpass filter (BPF) circuits, the n second digital signals into a plurality of outbound digital signals having a third data rate frequency. The coefficients for the taps of a digital BPF circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone component of the analog signal. The first data rate frequency is a first integer multiple of the third data rate frequency. The second data rate frequency is a second integer multiple of the third data rate frequency.

An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.

A digital interpolation filter delivering a series of output samples approximating a signal x(t) at sampling instants of the form (n+d)T s based on a series of input samples of the signal x(t) taken at sampling instants of the form nT s. Such a filter implements a transfer function in the Z-transform domain, H c<i/>d (Z−1), expressed as a linear combination between: a first transfer function H 1 d<i/>(Z−1) representing a Lagrange polynomial interpolation of the input samples implemented according to a Newton structure (100); and a second transfer function H 2 d (Z−1) representing another polynomial interpolation of the input samples implemented according to another structure comprising at least the Newton structure; the linear combination being a function of at least one real combination parameter c.

Trans-filter/Detectors are extremely sensitive circuits that recover exponentially modulated signals buried in noise. They can be used wherever Matched Filter/Coherent Detectors are used and operate at negative input signal-to-noise ratios to recover RADAR, SONAR, communications, or data signals, as well as reduce phase noise of precision oscillators. Input signal and noise is split into two paths where complementary derivatives are extracted. Outputs of the two paths are equal in amplitude and 180 degrees relative to each other at the band center frequency. The outputs are summed, causing stationary in-band noise to be reduced by cancellation while exponentially modulated signals are undiminished. Trans-filters are Linear Time Invariant circuits, have no noise x noise threshold and can be cascaded, increasing output signal-to-noise ratio prior to detection. Trans-filters are most sensitive to all types of digital modulation, producing easily detected polarized pulses synchronous with data transitions. Trans-filters do not require coherent conversion oscillators and complex synchronizing circuits.

Trans-filter/Detectors are extremely sensitive circuits that recover exponentially modulated signals buried in noise. They can be used wherever Matched Filter/Coherent Detectors are used and operate at negative input signal-to-noise ratios to recover RADAR, SONAR, communications, or data signals, as well as reduce phase noise of precision oscillators. Input signal and noise is split into two paths where complementary derivatives are extracted. Outputs of the two paths are equal in amplitude and 180 degrees relative to each other at the band center frequency. The outputs are summed, causing stationary in-band noise to be reduced by cancellation while exponentially modulated signals are undiminished. Trans-filters are Linear Time Invariant circuits, have no noise x noise threshold and can be cascaded, increasing output signal-to-noise ratio prior to detection. Trans-filters are most sensitive to all types of digital modulation, producing easily detected polarized pulses synchronous with data transitions. Trans-filters do not require coherent conversion oscillators and complex synchronizing circuits.

An example output driver includes a plurality of output circuits coupled in parallel between a first voltage supply node and a second voltage supply node. Each of the plurality of output circuits includes a differential input that is coupled to receive a logic signal of a plurality of logic signals and a differential output that is coupled to a common output node. The output driver further includes voltage regulator(s), coupled to the voltage supply node(s), and a current compensation circuit. The current compensation circuit includes a switch coupled in series with a current source, where the switch and the current source are coupled between the first voltage supply node and the second voltage supply node. An event detector is coupled to the switch to supply an enable signal and to control state of the enable signal based on presence of a pattern in the plurality of logic signals.

Systems, devices, and methods related to a sample rate converter (SRC) for implementing a rate conversion R are provided. The SRC receives input samples at an input rate F.sub.in and outputs samples at an output rate F.sub.out=F.sub.in×R, where R is a fractional value greater than 1. The SRC includes a plurality of filters to process the received input samples and a multiplier-adder block to generate the output samples based on respective delta values and outputs of the plurality of filters. The SRC further includes a plurality of buffers to buffer samples between the plurality of filters and the multiplier-adder block based at least in part on N buffer read pointers, where N is an integer greater than 1. The SRC further includes resampler control circuitry to generate N delta values of the delta values and the N buffer read pointers in parallel based on R.

A method is provided that includes performing, by a processor in response to a vector finite impulse response (VFIR) filter instruction, generating of a plurality of filter outputs using a plurality of coefficients and a plurality of sequential data elements, the plurality of coefficients specified by a coefficient operand of the VFIR filter instruction and the plurality of sequential data elements specified by a data operand of the VFIR filter instruction, and storing the filter outputs in a storage location specified by the VFIR filter instruction.

An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.