A digital filter circuit is described. The digital filter circuit includes a digital filter input, at least two finite impulse response (FIR) filter circuits, and a connection circuit. The digital filter input is configured to receive a digital input signal set having a data parallelism. The at least two FIR filter circuits are configured to process the digital input signal set at least partially. The at least two FIR filter circuits include a pre-adder sub-circuit, a convolution sub-circuit, and a post-adder sub-circuit, respectively. The connection circuit is configured to selectively connect the at least two FIR filter circuits based on the data parallelism of the digital input signal set.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

A Finite Impulse Response (FIR) filter is configured to minimize delay and maximize passband power by adjusting the filter coefficients applied to the sampled values. The FIR filter obtains an input signal and samples the input signal to generate a set of sampled input values. The FIR filter generates a set of filter coefficients, with each filter coefficient based on a corresponding sampled input value in the set of sample input values. The FIR filter selects a subset of sampled input values that have been most recently sampled from the input signal, and selects a subset of filter coefficients corresponding to sampled input values that are not the most recently sampled. The subset of sampled input values is combined with the subset of filter coefficients to generate an output value for the FIR filter.

A common sub-expression elimination method for simplifying hardware logic of a hardware filter circuit by eliminating a common sub-expression included in a plurality of sub-expressions is provided. Each of the sub-expressions includes a corresponding two or more of inputs constituting a plurality of coefficients used by the hardware filter circuit. The method is implemented on a computing device and includes: identifying for each coefficient of the plurality of coefficients, a combination of the inputs constituting the coefficient; counting occurrences of the sub-expressions in each of the coefficients; identifying one or more of the sub-expressions having a maximum one of the counts and including the corresponding two or more of the inputs; selecting one of the one or more of the sub-expressions as the common sub-expression; eliminating the common sub-expression; and repeating these steps to eliminate more of the sub-expressions common to multiple ones of the coefficients.

A common sub-expression elimination method for simplifying hardware logic of a hardware filter circuit by eliminating a common sub-expression included in a plurality of sub-expressions is provided. Each of the sub-expressions includes a corresponding two or more of inputs constituting a plurality of coefficients used by the hardware filter circuit. The method is implemented on a computing device and includes: identifying for each coefficient of the plurality of coefficients, a combination of the inputs constituting the coefficient; counting occurrences of the sub-expressions in each of the coefficients; identifying one or more of the sub-expressions having a maximum one of the counts and including the corresponding two or more of the inputs; selecting one of the one or more of the sub-expressions as the common sub-expression; eliminating the common sub-expression; and repeating these steps to eliminate more of the sub-expressions common to multiple ones of the coefficients.

Circuitry that accepts a data input and an enable input, and generates an output sum based on the data input includes an input stage circuit that includes an input register. The input register accepts the enable input. The circuitry further includes a systolic register operatively connected to the input stage circuit, and the systolic register is operated without any enable connection. The circuitry further includes a multiplier connected to the systolic register, which is configured to generate a product value. The circuitry further includes an output stage circuit that includes an adder that calculates the output sum based least in part on the product value.

Circuitry that accepts a data input and an enable input, and generates an output sum based on the data input includes an input stage circuit that includes an input register. The input register accepts the enable input. The circuitry further includes a systolic register operatively connected to the input stage circuit, and the systolic register is operated without any enable connection. The circuitry further includes a multiplier connected to the systolic register, which is configured to generate a product value. The circuitry further includes an output stage circuit that includes an adder that calculates the output sum based least in part on the product value.

A method of increasing the sample rate of a digital signal by creating intermediate sample points between adjacent neighbouring sample points comprising the step of populating each of the intermediate sample points depending on a weighted influence of a predetermined number of the neighbouring sample points, the weighted influence being calculated by representing the digital signal or filter at the predetermined number of sample points at least in part by its cosine components, which are each represented by absolute values of a cosine function in the time domain substantially limited to half a waveform cycle at its mid-point; combining the aforementioned cosine components at each of the neighbouring sample points to obtain waveforms at each of the neighboring sample points; determining values for each of the waveforms at the intermediate sample points and combining the determined values at the intermediate sample point to derive the weighted influence.

A method of processing a digital signal includes providing a digital filter including neighbouring sample points and performing a sample rate increase on the digital filter to provide intermediate sample points between adjacent neighbouring sample points, said intermediate points being populated dependent on a weighted influence determined in the time domain of a predetermined number of the neighbouring sample points. The digital filter is applied to the signal where: i) one of the neighbouring sample points of the filter is applied to a corresponding sample point of the signal; ii) offset and neighbouring sample points of the signal are defined either side of the corresponding sample point, said offset points being offset in the time domain relative to the respective neighbouring sample points of the filter; and iii) the neighbouring sample points of the filter are applied to respective of the offset and neighbouring sample points of the signal.

A method of processing a digital signal includes providing a digital filter including neighbouring sample points and performing a sample rate increase on the digital filter to provide intermediate sample points between adjacent neighbouring sample points, said intermediate points being populated dependent on a weighted influence determined in the time domain of a predetermined number of the neighbouring sample points. The digital filter is applied to the signal where: i) one of the neighbouring sample points of the filter is applied to a corresponding sample point of the signal; ii) offset and neighbouring sample points of the signal are defined either side of the corresponding sample point, said offset points being offset in the time domain relative to the respective neighbouring sample points of the filter; and iii) the neighbouring sample points of the filter are applied to respective of the offset and neighbouring sample points of the signal.