Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

The disclosure relates to technology for a fully differential adjustable gain device that includes differential input terminals, differential output terminals, fully differential signal processing circuitry, and first and second cross-coupled segments. The first cross-coupled segment is coupled between differential input terminals of the fully differential adjustable gain device and a negative input of the fully differential signal processing circuitry. The second cross-coupled segment is coupled between differential input terminals of the fully differential adjustable gain device and a positive input of the fully differential signal processing circuitry. The fully differential adjustable gain device has a gain that is adjustable by adjusting values of the first and second cross-coupled segments, while maintaining a substantially consistent frequency response and a substantially consistent input impedance of the fully differential adjustable gain device, so long as a specified relationship between values of the first and second cross-coupled segments is kept substantially constant.

A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

Embodiments of methods and systems for attenuator phase compensation are described. In an embodiment, a method for attenuator phase compensation involves determining a phase compensation value for an attenuator based on an attenuation configuration of the attenuator and performing phase compensation according to the phase compensation value to maintain a constant phase response.

A programmable resistor can provide discrete logarithmic (linear-in-dB) gain control. It can include multiple like programmable resistor subnetworks or cells, such as can be connected in parallel, such as according to a decoding scheme. The subnetworks can be configured to cover a subrange such as [0 dB, 6 dB) relative to the maximum resistance value. Coarse increments of 6 dB can be further added to this range by successively doubling the number of subnetworks that are connected in parallel. An additional decoder help ensure a linear control curve, free of dead zones or other nonlinearities. The programmable resistor can be suitable for use in such circuits as programmable-gain amplifiers, filters, or more complex networks, such as where the resistance can be programmed as a function of a digital code. An example including a tuning circuit for a variable gain active filter is described.

A method and apparatus for modifying or controlling a resonator connected to a signal loop having an input, an output, and a closed loop frequency response. The signal loop has a primary resonator having a primary frequency response. There is at least one adjustable resonator having an adjustable frequency and a secondary Q-factor. An adjustable scaling block applies a gain factor. A controller is connected to the at least one adjustable resonator and the adjustable scaling block. The controller has instructions to adjust the closed loop frequency response toward a desired closed loop frequency response by controlling the adjustable frequency of the at least one adjustable resonator and the gain factor of the adjustable scaling block.

A method and apparatus for modifying or controlling a resonator connected to a signal loop having an input, an output, and a closed loop frequency response. The signal loop has a primary resonator having a primary frequency response. There is at least one adjustable resonator having an adjustable frequency and a secondary Q-factor. An adjustable scaling block applies a gain factor. A controller is connected to the at least one adjustable resonator and the adjustable scaling block. The controller has instructions to adjust the closed loop frequency response toward a desired closed loop frequency response by controlling the adjustable frequency of the at least one adjustable resonator and the gain factor of the adjustable scaling block.

A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.