A multiplexer includes a filter (10) arranged between a common terminal and an input/output terminal (110) and configured to pass a radio frequency signal in a first frequency band, and a filter (20) arranged between the common terminal and an input/output terminal (120) and configured to pass a radio frequency signal in a second frequency band. The filter includes series arm circuits (31 and 32) connected in series, a series arm circuit (33) connected in parallel to the series arm circuit (32), and a parallel arm circuit. The series arm circuit (32) includes a series arm resonator that is an acoustic wave resonator. The series arm circuit (33) includes a switch arranged on a second path connecting nodes. In a CA mode, the switch is OFF. In a non-CA mode, the switch is ON.

A filter device includes a terminal, a switch that includes a common terminal and selection terminals and switches a connection of the common terminal to one of the selection terminals, a series arm resonator, and filter circuits. The filter circuits are connected to one end of the series arm resonator. The common terminal is connected to the terminal. One of the selection terminals is connected between one end of the series arm resonator and the filter circuits. Another one of the selection terminals is connected to the other end of the series arm resonator.

A radio-frequency filter includes a first series-arm circuit and a second series-arm circuit that is on a circuit path closer to the output terminal than the first series-arm circuit. A first parallel-arm circuit is connected to a ground and a node on the path between the first series-arm circuit and the second series-arm circuit. The first series-arm circuit includes a first series-arm resonator, and a first switch element, the first switch element including first semiconductor elements arranged in series. The second series-arm circuit includes a second series-arm resonator, and a second switch element, the second switch element including at least one second semiconductor element. A first stack number being higher than a second stack number, the first stack number being a number of the first semiconductor elements and the second stack number being a number of the one or more second semiconductor elements.

A filter includes: a series-arm circuit; a first parallel-arm circuit connected to a ground and a node; and a second parallel-arm circuit connected to the ground and a node. The first parallel-arm circuit includes a parallel-arm resonator, and a first switch circuit. The second parallel-arm circuit includes a parallel-arm resonator, and a second switch circuit. The first switch circuit includes a first switch. The second switch circuit includes a second switch. A voltage across the first switch is lower than a voltage across the second switch. A stack count of the first switch is lower than a stack count of the second switch.

An acoustic filter apparatus is provided. In examples discussed herein, the acoustic filter apparatus includes an acoustic ladder network configured to pass a signal in a series resonance frequency and block the signal in a number of parallel resonance frequencies. The acoustic ladder network is coupled to a microelectromechanical systems (MEMS) switch circuit that includes a number of MEMS switches. The MEMS switches may be selectively controlled (e.g., closed and/or opened) to cause a modification to a selected parallel resonance frequency(s) among the parallel resonance frequencies. As such, it may be possible to flexibly configure the parallel resonance frequencies of the acoustic ladder network based on application scenarios. Further, by employing the MEMS switches having improved figure-of-merit (FOM) over conventional silicon-on-insulator (SOI) switches, it may be possible to reconfigure the parallel resonance frequencies with reduced insertion loss, thus helping to improve performance of the acoustic filter apparatus.

An apparatus has advanced amplifier Classes and low pass filter technologies for using software generated ascending or level waveforms that are effective when applying cardiac defibrillation and cardioversion waveforms which significantly reduce damage to the heart muscle. The apparatus comprises a waveform energy control system for delivering software generated waveforms comprising differentially driven Class D and Class B amplifier sections, wherein the Class D amplifier section produces Phase 1 ascending waveforms and has a programmable lowpass filter (LPF) and wherein the Class B amplifier section delivers hard-switched Phase 2 waveforms.

An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.

Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.

An acoustic structure is provided. The acoustic structure includes an acoustic resonator structure configured to resonate in a series resonance frequency (e.g., passband frequency) to pass a signal, or cause a series capacitance to block the signal in a parallel resonance frequency (e.g., stopband frequency). The parallel resonance frequency may become higher than the series resonance frequency when the tunable capacitance is lesser than or equal to two times of the series capacitance (C.sub.Tune2C.sub.0), or lower than the series resonance frequency when the tunable capacitance is greater than two times of the series capacitance (C.sub.Tune>2C.sub.0). In this regard, the acoustic structure can be configured to include a tunable reactive circuit to generate the tunable capacitance (C.sub.Tune) to adjust the parallel resonance frequency. As such, it may be possible to flexibly configure the acoustic resonator structure to block the signal in desired stopband frequencies.

An acoustic impedance transformation circuit and related apparatus are provided. In aspects discussed herein, the acoustic impedance transformation circuit can be configured to transform an input impedance into an output impedance higher than the input impedance. In this regard, the acoustic impedance transformation circuit can be provided in an apparatus to enable impedance matching between two electrical circuits. As a result, it may be possible to reduce signal reflection resulting from impedance mismatch between the two circuits, thus helping to improve performance of the apparatus.