A low-power retention flip-flop is provided. The low-power retention flip-flop may include: a master latch configured to output an input signal based on first control signals; a slave latch configured to output the signal from the master latch based on second control signals; and a control logic configured to generate the first control signals based on a clock signal, and provide the generated first control signals to the master latch, and generate the second control signals based on the clock signal and a power down mode signal, and provide the generated second control signals to the slave latch.

A low-power retention flip-flop is provided. The low-power retention flip-flop may include: a master latch configured to output an input signal based on first control signals; a slave latch configured to output the signal from the master latch based on second control signals; and a control logic configured to generate the first control signals based on a clock signal, and provide the generated first control signals to the master latch, and generate the second control signals based on the clock signal and a power down mode signal, and provide the generated second control signals to the slave latch.

The present disclosure relates to a latch circuit and a latch method, and an electronic device, and relates to the technical field of integrated circuits. The latch circuit includes: a transmission module, a latch module, and a control module, wherein the transmission module is configured to transmit an input signal to the latch module; the latch module is configured to latch the input signal or output the input signal when a set signal or a reset signal is at a low level; and the control module is configured to perform control, such that a current leakage path cannot be formed between the transmission module and the latch module when the set signal or the reset signal is at a high level.

A switch control circuit and a switch control method are provided. The switch control circuit includes a load, an inductor, a control switch, and a sensing resistance connected in series to an input power; an integrator that integrates a sensing voltage and a load current setting voltage to generate an integrated signal; a comparator that compares the integrated signal and a bias voltage; a switch driver that controls the control switch based on an output of the comparator and an output of an off time controller; and a gate sensor that outputs, to the integrator, a gate sensing signal that senses a time when an input of a gate terminal of the control switch becomes a low level. An integration operation is started from a position in which the integrated signal is located lower than the bias voltage, when an input of the gate terminal becomes a high level.

A switch control circuit and a switch control method are provided. The switch control circuit includes a load, an inductor, a control switch, and a sensing resistance connected in series to an input power; an integrator that integrates a sensing voltage and a load current setting voltage to generate an integrated signal; a comparator that compares the integrated signal and a bias voltage; a switch driver that controls the control switch based on an output of the comparator and an output of an off time controller; and a gate sensor that outputs, to the integrator, a gate sensing signal that senses a time when an input of a gate terminal of the control switch becomes a low level. An integration operation is started from a position in which the integrated signal is located lower than the bias voltage, when an input of the gate terminal becomes a high level.

An apparatus is disclosed that includes a common drain, a common source, and a common gate, respectively, of the power semiconductor device, and paralleled transistor cells of the power semiconductor device. In various examples, a configuration of a gate structure of a first respective transistor cell coupled with the common gate is different than a configuration of a gate structure of a second respective transistor cell coupled with the common gate. Alternatively or additionally, in various examples, a configuration of a structure coupled between a first portion of the paralleled transistor cells and the common gate is different than a configuration of a structure coupled between the second portion of the paralleled transistor cells and the common gate.

An apparatus is disclosed that includes a common drain, a common source, and a common gate, respectively, of the power semiconductor device, and paralleled transistor cells of the power semiconductor device. In various examples, a configuration of a gate structure of a first respective transistor cell coupled with the common gate is different than a configuration of a gate structure of a second respective transistor cell coupled with the common gate. Alternatively or additionally, in various examples, a configuration of a structure coupled between a first portion of the paralleled transistor cells and the common gate is different than a configuration of a structure coupled between the second portion of the paralleled transistor cells and the common gate.

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

A switching component and switch assembly. The switching component comprises a first control node, a common node, a plurality of intermediate nodes, a second control node, and a capacitive node; a plurality of transistors connected in series between the control node and the common node, one of the plurality of intermediate nodes being defined between each series connected pair of transistors, each transistor of the plurality of transistors having a gate coupled to the second control node; and a plurality of capacitive components, one capacitive component being coupled between each intermediate node and the capacitive node, a voltage at the capacitive node being configured to be varied with a voltage at the second control node such that, at each intermediate node, the capacitive component is configured to accrue an opposite charge to the transistors.