A flip-flop circuit includes a clock generator configured to generate first and second clock signals having different phases relative to each other, and a master-slave latch circuit including master and slave latches. The master latch includes a scan path configured to output a scan path signal in response to a scan enable signal and a scan input signal, and a data path configured to output a first latch signal in response to a data signal and the scan path signal. A feedback path is provided, which includes a tri-state inverter responsive to the first and second clock signals. The tri-state inverter has an input terminal connected to an output terminal of the data path and an output terminal connected to a node of the scan path.

A system includes a sensor circuit configured to sense a parameter of a power system having an operating voltage greater than a voltage rating of the sensor circuit, an optical communications circuit configured to receive a sensor signal from the sensor circuit and to generate an optical communications signal therefrom, and an optical power supply circuit configured to receive an optical input, to generate electrical power from the received optical input and to supply the generated electrical power to the sensor circuit and the optical communications circuit. A driver circuit may be configured to generate a first control signal applied to a control terminal of the power semiconductor switch, and the optical power supply circuit may be configured to supply the generated electrical power to the sensor circuit, the optical communications circuit and the driver circuit.

A system includes a sensor circuit configured to sense a parameter of a power system having an operating voltage greater than a voltage rating of the sensor circuit, an optical communications circuit configured to receive a sensor signal from the sensor circuit and to generate an optical communications signal therefrom, and an optical power supply circuit configured to receive an optical input, to generate electrical power from the received optical input and to supply the generated electrical power to the sensor circuit and the optical communications circuit. A driver circuit may be configured to generate a first control signal applied to a control terminal of the power semiconductor switch, and the optical power supply circuit may be configured to supply the generated electrical power to the sensor circuit, the optical communications circuit and the driver circuit.

A pulse-based flip flop circuit includes; a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving one of a data signal and the scan input signal in response to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes; a direct path providing a clock signal as a direct path input to a NAND circuit, a delay path including a number of stages configured to delay the clock signal and provide a delayed clock signal as a delay path input to NAND circuit, wherein the NAND circuit performs a NAND operation on the direct path input and the delay path input to generate the inverted pulse signal, and a feedback path providing the pulse signal to a first stage among the number of stages of the delay path.

A pulse-based flip flop circuit includes; a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving one of a data signal and the scan input signal in response to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes; a direct path providing a clock signal as a direct path input to a NAND circuit, a delay path including a number of stages configured to delay the clock signal and provide a delayed clock signal as a delay path input to NAND circuit, wherein the NAND circuit performs a NAND operation on the direct path input and the delay path input to generate the inverted pulse signal, and a feedback path providing the pulse signal to a first stage among the number of stages of the delay path.

A load driving circuit includes a switch circuit and a linear circuit connected in series. The switch circuit has a switching transistor and converts an input voltage into a first output voltage. The linear circuit has a linear device and provides a driving voltage and a driving current for driving the load. The driving circuit controls the switching transistor according to a feedback signal indicative of conducting state of the linear device.

A load driving circuit includes a switch circuit and a linear circuit connected in series. The switch circuit has a switching transistor and converts an input voltage into a first output voltage. The linear circuit has a linear device and provides a driving voltage and a driving current for driving the load. The driving circuit controls the switching transistor according to a feedback signal indicative of conducting state of the linear device.

This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111 P) is configured to output a first intermediate voltage (V.sub.SAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance. The voltage clamp (114P) is enabled by a reset condition (RST) for the audio driving circuit.

This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111 P) is configured to output a first intermediate voltage (V.sub.SAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance. The voltage clamp (114P) is enabled by a reset condition (RST) for the audio driving circuit.

A solid state driver to adapt current ripple characteristics therein, at least partially based on operating characteristics of a solid state lighting device operated by the driver, is provided. The driver senses operating voltage, operating current, or a combination of operating voltage and operating current of a solid state lighting device. The driver stores pre-determined current ripple percentage settings in a data structure, for example, in a controller circuit. The driver selects and implements one of the pre-determined current ripple percentage settings based on one or more of the sensed operating characteristics of the solid state lighting device, to improve efficiency, to reduce the operating frequency, and/or to lower the operating temperature of one or more components of the driver.