Embodiments of this application disclose an RC oscillator. The RC oscillator may amplify a difference between a first voltage and a second voltage by using a first amplifier and a second amplifier. The first amplifier may include a first amplification circuit and a second amplification circuit. The first amplification circuit and the second amplification circuit may share a same voltage-current conversion circuit. The RC oscillator disclosed in the embodiments of this application can not only avoid noise introduced by the first amplifier, but also reduce internal noise of the RC oscillator. This reduces a jitter of a clock signal.

A comparator includes an input pair circuit, an isolation circuit, and a latch circuit. The input pair circuit receives first and second input signals to generate first and second signals. The isolation circuit is selectively turned on according to a clock signal to transmit the first signal from the input pair circuit to a first output node and transmit the second signal from the input pair circuit to a second output node. The latch circuit adjusts a level of the first output node to generate a first output signal, adjusts a level of the second output node to generate a second output signal, and selectively resets the levels of the first and the second output nodes according to the clock signal. When the latch circuit resets the levels of the first and the second output nodes, the isolation circuit is not turned on.

A comparator includes an input pair circuit, an isolation circuit, and a latch circuit. The input pair circuit receives first and second input signals to generate first and second signals. The isolation circuit is selectively turned on according to a clock signal to transmit the first signal from the input pair circuit to a first output node and transmit the second signal from the input pair circuit to a second output node. The latch circuit adjusts a level of the first output node to generate a first output signal, adjusts a level of the second output node to generate a second output signal, and selectively resets the levels of the first and the second output nodes according to the clock signal. When the latch circuit resets the levels of the first and the second output nodes, the isolation circuit is not turned on.

An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage.

An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage.

A Schmitt trigger voltage comparator circuit is provided including a voltage reference input, a current source having a first voltage controlled current source connected to the voltage reference input and a second voltage controlled current source connected to a signal input for converting the signal input to a input current and the voltage reference input to a reference current, a current mirror having an input connected to the output of the first voltage controlled current source configured and arranged to invert the direction of the first current and an output of the current mirror connected to the output of the second voltage controlled current source, and a sequence controller for generating digital signals to control a first plurality of switches and a second plurality of switches. The first plurality of switches control the first and second voltage controlled current sources and the second plurality of switches control the current mirror.

A microelectronic circuit comprises a plurality of logic units and register circuits arranged into a plurality of processing paths. At least one monitor circuit (404) is associated with a first register circuit (301), said monitor circuit (404) being configured to produce a timing event observation signal as a response to a change in a digital value at an input (D) of the first register circuit (301) that took place later than an allowable time limit defined by a triggering signal (CP) to said first register circuit (301). A first processing path goes through a first logic unit (501) to said first register circuit (301) and is a delay critical processing path due to an amount of delay that it is likely to generate. The microelectronic circuit comprises a controllable data event injection point (503) for controllably generating a change of a digital value propagating to said first logic unit (501) irrespective of what other data is processed on said first processing path. Said microelectronic circuit is configured to freeze a first digital value stored in said first register circuit (301) for a time during which the change generated through said controllable data event injection point (503) propagates to said first register circuit.

According to embodiments of the present invention, a circuit is provided. The circuit includes a first set of transistors configured to receive one or more input signals provided to the circuit, and a second set of transistors electrically coupled to each other, wherein the second set of transistors is configured to provide one or more output signals of the circuit, wherein the first set of transistors and the second set of transistors are electrically coupled to each other, and wherein, for each transistor of the first set of transistors and the second set of transistors, the transistor is configured to drive a load associated with the transistor and has an aspect ratio that is sized larger than an aspect ratio of a transistor that is optimized for driving the load.

To provide a filter circuit and a semiconductor device capable of preventing circuit malfunction even when power supply voltage fluctuates. A filter circuit includes: a latch circuit configured to latch a set signal input to a first input terminal and a reset signal input to a second input terminal, respectively; and a rise adjustment unit configured to make a rise time of the set signal or the reset signal at power-on shorter than a time specified by a time constant circuit arranged in a preceding stage of the latch circuit.

To provide a filter circuit and a semiconductor device capable of preventing circuit malfunction even when power supply voltage fluctuates. A filter circuit includes: a latch circuit configured to latch a set signal input to a first input terminal and a reset signal input to a second input terminal, respectively; and a rise adjustment unit configured to make a rise time of the set signal or the reset signal at power-on shorter than a time specified by a time constant circuit arranged in a preceding stage of the latch circuit.