A signal conditioner for conditioning a differential oscillation signal into a compliant clock signal including first and second signal paths and a coincident gate. The first signal path toggles a first binary signal in response to the differential oscillation signal when the differential oscillation signal reaches a small amplitude level. The second signal path toggles a second binary signal in response to the differential oscillation signal only when the differential oscillation signal reaches a large amplitude level that is greater than the small amplitude level. The coincident gate toggles the clock signal high only when the first and second binary signals are both high, and toggles the clock signal low only when the first and second binary signals are both low. When the clock signal begins toggling, it may skip one or more cycles but is nonetheless compliant in terms of timing and amplitude.

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks on-the-fly, e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks on-the-fly, e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

In described examples, a ring oscillator includes a series of N stages in a first ring. Each stage includes a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring. N is a positive odd-numbered integer of at least three. A series of N level shifters in a second ring are respectively connected to the N stages. Each level shifter receives a respective clock output from a respective output terminal of a stage to which it is connected and generates a respective boosted clock output in response thereto. The boosted clock output is coupled to control an impedance state of a next one of the level shifters in the second ring.

In described examples, a ring oscillator includes a series of N stages in a first ring. Each stage includes a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring. N is a positive odd-numbered integer of at least three. A series of N level shifters in a second ring are respectively connected to the N stages. Each level shifter receives a respective clock output from a respective output terminal of a stage to which it is connected and generates a respective boosted clock output in response thereto. The boosted clock output is coupled to control an impedance state of a next one of the level shifters in the second ring.

A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.

A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.

A signal conditioner for conditioning a differential oscillation signal into a compliant clock signal including first and second signal paths and a coincident gate. The first signal path toggles a first binary signal in response to the differential oscillation signal when the differential oscillation signal reaches a small amplitude level. The second signal path toggles a second binary signal in response to the differential oscillation signal only when the differential oscillation signal reaches a large amplitude level that is greater than the small amplitude level. The coincident gate toggles the clock signal high only when the first and second binary signals are both high, and toggles the clock signal low only when the first and second binary signals are both low. When the clock signal begins toggling, it may skip one or more cycles but is nonetheless compliant in terms of timing and amplitude.

An oscillator capable of quick startup is provided. A transistor is provided between an output terminal of a certain stage inverter and an input terminal of the following stage inverter included in the voltage controlled oscillator. With the use of the on resistance of the transistor, the oscillation frequency of the clock signal is controlled. While supply of the power supply voltage is stopped, a signal that is input to the input terminal of the inverter just before supply of the power supply voltage is stopped is stored by turning off the transistor. This operation makes it possible to immediately output a clock signal that has the same frequency as that before supply of the power supply voltage is stopped at the time when the power supply voltage is supplied again.

An oscillator capable of quick startup is provided. A transistor is provided between an output terminal of a certain stage inverter and an input terminal of the following stage inverter included in the voltage controlled oscillator. With the use of the on resistance of the transistor, the oscillation frequency of the clock signal is controlled. While supply of the power supply voltage is stopped, a signal that is input to the input terminal of the inverter just before supply of the power supply voltage is stopped is stored by turning off the transistor. This operation makes it possible to immediately output a clock signal that has the same frequency as that before supply of the power supply voltage is stopped at the time when the power supply voltage is supplied again.