Some embodiments include a high voltage, high frequency switching circuit. The switching circuit may include a high voltage switching power supply that produces pulses having a voltage greater than 1 kV and with frequencies greater than 10 kHz and an output. The switching circuit may also include a resistive output stage electrically coupled in parallel with the output and between the output stage and the high voltage switching power supply, the resistive output stage comprising at least one resistor that discharges a load coupled with the output. In some embodiments, the resistive output stage may be configured to discharge over about 1 kilowatt of average power during each pulse cycle. In some embodiments, the output can produce a high voltage pulse having a voltage greater than 1 kV and with frequencies greater than 10 kHz with a pulse fall time less than about 400 ns.

Some embodiments include a high voltage, high frequency switching circuit. The switching circuit may include a high voltage switching power supply that produces pulses having a voltage greater than 1 kV and with frequencies greater than 10 kHz and an output. The switching circuit may also include a resistive output stage electrically coupled in parallel with the output and between the output stage and the high voltage switching power supply, the resistive output stage comprising at least one resistor that discharges a load coupled with the output. In some embodiments, the resistive output stage may be configured to discharge over about 1 kilowatt of average power during each pulse cycle. In some embodiments, the output can produce a high voltage pulse having a voltage greater than 1 kV and with frequencies greater than 10 kHz with a pulse fall time less than about 400 ns.

An electrostatic protection circuit is disclosed. The electrostatic protection circuit includes delay circuitry coupled between a supply voltage node and a fixed voltage node. The electrostatic protection circuit also includes latch circuitry made up of current-limiting circuitry that includes a gallium arsenide transistor and a latch. The current-limiting circuitry and the latch are coupled between the supply voltage node and the fixed voltage node, and the current-limiting circuitry is also coupled to the delay circuitry. The electrostatic protection circuit further includes discharge circuitry coupled between the supply voltage node and the fixed voltage node and to the latch, wherein the latch is configured to drive the discharge circuitry to short the supply voltage node to the fixed voltage node during an electrostatic discharge event, and the current-limiting circuitry is configured to limit latch current from the supply voltage node to the latch during normal operation.

An electrostatic protection circuit is disclosed. The electrostatic protection circuit includes delay circuitry coupled between a supply voltage node and a fixed voltage node. The electrostatic protection circuit also includes latch circuitry made up of current-limiting circuitry that includes a gallium arsenide transistor and a latch. The current-limiting circuitry and the latch are coupled between the supply voltage node and the fixed voltage node, and the current-limiting circuitry is also coupled to the delay circuitry. The electrostatic protection circuit further includes discharge circuitry coupled between the supply voltage node and the fixed voltage node and to the latch, wherein the latch is configured to drive the discharge circuitry to short the supply voltage node to the fixed voltage node during an electrostatic discharge event, and the current-limiting circuitry is configured to limit latch current from the supply voltage node to the latch during normal operation.

Some embodiments include a high voltage, high frequency switching circuit. The switching circuit may include a high voltage switching power supply that produces pulses having a voltage greater than 1 kV and with frequencies greater than 10 kHz and an output. The switching circuit may also include a resistive output stage electrically coupled in parallel with the output and between the output stage and the high voltage switching power supply, the resistive output stage comprising at least one resistor that discharges a load coupled with the output. In some embodiments, the resistive output stage may be configured to discharge over about 1 kilowatt of average power during each pulse cycle. In some embodiments, the output can produce a high voltage pulse having a voltage greater than 1 kV and with frequencies greater than 10 kHz with a pulse fall time less than about 400 ns.

Some embodiments include a high voltage, high frequency switching circuit. The switching circuit may include a high voltage switching power supply that produces pulses having a voltage greater than 1 kV and with frequencies greater than 10 kHz and an output. The switching circuit may also include a resistive output stage electrically coupled in parallel with the output and between the output stage and the high voltage switching power supply, the resistive output stage comprising at least one resistor that discharges a load coupled with the output. In some embodiments, the resistive output stage may be configured to discharge over about 1 kilowatt of average power during each pulse cycle. In some embodiments, the output can produce a high voltage pulse having a voltage greater than 1 kV and with frequencies greater than 10 kHz with a pulse fall time less than about 400 ns.

An electrostatic protection circuit is disclosed. The electrostatic protection circuit includes delay circuitry coupled between a supply voltage node and a fixed voltage node. The electrostatic protection circuit also includes latch circuitry made up of current-limiting circuitry that includes a gallium arsenide transistor and a latch. The current-limiting circuitry and the latch are coupled between the supply voltage node and the fixed voltage node, and the current-limiting circuitry is also coupled to the delay circuitry. The electrostatic protection circuit further includes discharge circuitry coupled between the supply voltage node and the fixed voltage node and to the latch, wherein the latch is configured to drive the discharge circuitry to short the supply voltage node to the fixed voltage node during an electrostatic discharge event, and the current-limiting circuitry is configured to limit latch current from the supply voltage node to the latch during normal operation.

An electrostatic protection circuit is disclosed. The electrostatic protection circuit includes delay circuitry coupled between a supply voltage node and a fixed voltage node. The electrostatic protection circuit also includes latch circuitry made up of current-limiting circuitry that includes a gallium arsenide transistor and a latch. The current-limiting circuitry and the latch are coupled between the supply voltage node and the fixed voltage node, and the current-limiting circuitry is also coupled to the delay circuitry. The electrostatic protection circuit further includes discharge circuitry coupled between the supply voltage node and the fixed voltage node and to the latch, wherein the latch is configured to drive the discharge circuitry to short the supply voltage node to the fixed voltage node during an electrostatic discharge event, and the current-limiting circuitry is configured to limit latch current from the supply voltage node to the latch during normal operation.

A semiconductor integrated circuit includes a clock recovery circuit that receive a multi-level pulse-amplitude modulated signal and to recover a clock signal. The clock recovery circuit includes a generation circuit and an oscillator. The generation circuit includes a plurality of comparators and pulse generators and a pulse summing circuit. The plurality of comparators and pulse generators compare the multi-level pulse-amplitude modulated signal with a plurality of threshold values to generate a plurality of pulses according to a plurality of comparison results. The pulse summing circuit generates a synthetic pulse based on the generated plurality of pulses. The oscillator oscillates in synchronization with the synthetic pulse to generate the clock signal.

A semiconductor integrated circuit includes a clock recovery circuit that receive a multi-level pulse-amplitude modulated signal and to recover a clock signal. The clock recovery circuit includes a generation circuit and an oscillator. The generation circuit includes a plurality of comparators and pulse generators and a pulse summing circuit. The plurality of comparators and pulse generators compare the multi-level pulse-amplitude modulated signal with a plurality of threshold values to generate a plurality of pulses according to a plurality of comparison results. The pulse summing circuit generates a synthetic pulse based on the generated plurality of pulses. The oscillator oscillates in synchronization with the synthetic pulse to generate the clock signal.