A method and apparatus for generating a drive signal for driving a resolver sensor are provided. The method and apparatus implement a drive signal to be input to a resolver sensor. The method and apparatus perform counting in association with an incoming square wave signal and implement a drive signal after confirming that a specific point corresponding to a preset condition of the incoming square wave signal arrives.

According to one embodiment, a power supply circuit includes a smoothing capacitor that is charged with a charge current from an output transistor and outputs a voltage as an output voltage; a control loop that controls a conduction state of the output transistor depending on a difference value between the output voltage and a reference voltage; and a gain adjustment circuit that adjusts a gain of the control loop depending on magnitude of the charge current after the charge starts.

According to one embodiment, a power supply circuit includes a smoothing capacitor that is charged with a charge current from an output transistor and outputs a voltage as an output voltage; a control loop that controls a conduction state of the output transistor depending on a difference value between the output voltage and a reference voltage; and a gain adjustment circuit that adjusts a gain of the control loop depending on magnitude of the charge current after the charge starts.

An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage.

Various techniques are provided to correct the duty cycles and convert differential clock signals in synchronized systems. In one example, a method includes receiving an input differential clock signal having a distorted duty cycle. The method also includes adjusting the input differential clock signal to provide an output differential clock signal with a corrected duty cycle. The adjusting is performed in response to signals provided by a differential amplifier and a common mode amplifier of an analog feedback circuit receiving the output differential clock signal. Additional methods and systems are also provided.

Various techniques are provided to correct the duty cycles and convert differential clock signals in synchronized systems. In one example, a method includes receiving an input differential clock signal having a distorted duty cycle. The method also includes adjusting the input differential clock signal to provide an output differential clock signal with a corrected duty cycle. The adjusting is performed in response to signals provided by a differential amplifier and a common mode amplifier of an analog feedback circuit receiving the output differential clock signal. Additional methods and systems are also provided.

A pulse signal compensation circuit of a pulse generator can include a pulse measurement circuit and a compensation generator circuit. The pulse measurement circuit can be configured to receive a plurality of pulse signals and to generate an average duty cycle or pulse overlap signal proportional to the duty cycle or pulse overlap of the plurality of pulses. The compensation generator circuit can be configured to receive the average duty cycle or pulse overlap signal and generate a duty cycle or pulse overlap compensation signal based on the average duty cycle or pulse overlap signal. The compensation signal can be utilized to adjust the duty cycle, amount of positive or negative pulse width overlap, and or the like of the plurality of pulse signals.

A receiver can include a first set of one or more amplifier stages configured to amplify input signals in a plurality of communication bands. The receiver can further include a second and third set of one or more amplifier stages. The second set of one or more amplifier stages can be configured to selectively receive the input signals in the plurality of communication bands amplified by the first set of one or more amplifier stages and to amplify one or more input signals in a first one of the plurality of communication bands. Alternatively, the third set of one or more amplifier stages can be configured to selectively receive the input signals in the plurality of communication bands amplified by the first set of one or more amplifier stages and to amplify one or more input signals in a second one of the plurality of communication bands. A first set of one or more mixers can be configured to receive the input signals in the first communication band amplified by the second set of one or more amplifier stages, to receive one or more local oscillator signals for the first communication band, and to generate a baseband signal from a frequency difference of the signal of the first communication band and the one or more local oscillator signals for the first communication band. A second set of one or more mixers can be configured to receive the input signal in the second communication band amplified by the third set of one or more amplifier stages, to receive one or more local oscillator signals for the second communication band, and to generate a baseband signal of the second communication band.

A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs.

A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs.