An oscillator including two sequentially connected pulse generation circuits is disclosed. Each pulse generation circuit includes a charge/discharge circuit and a switch circuit and outputs a first or second signal depending on an input signal. The switch circuit controls the charge/discharge circuit so that the latter is charged when the input signal is at a first level and discharged when the input signal is at a second level higher than the first level. When the input signal is at the first level, the first signal is at the first level and the second signal is at the second level. When the input signal is at the second level, the first signal is at the second level and the second signal is at the first level. Upon completion of discharge of the charge/discharge circuit, the first signal changes to the first level and the second signal changes to the second level.

An oscillator including two sequentially connected pulse generation circuits is disclosed. Each pulse generation circuit includes a charge/discharge circuit and a switch circuit and outputs a first or second signal depending on an input signal. The switch circuit controls the charge/discharge circuit so that the latter is charged when the input signal is at a first level and discharged when the input signal is at a second level higher than the first level. When the input signal is at the first level, the first signal is at the first level and the second signal is at the second level. When the input signal is at the second level, the first signal is at the second level and the second signal is at the first level. Upon completion of discharge of the charge/discharge circuit, the first signal changes to the first level and the second signal changes to the second level.

An example analog-test-bus (ATB) apparatus includes a plurality of comparator circuits, each having an output port, and a pair of input ports of opposing polarity including an inverting port and a non-inverting port, a plurality of circuit nodes to be selectively connected to the input ports of a first polarity, and at least one digital-to-analog converter (DAC) to drive the input ports of the plurality of comparator circuits. The apparatus further includes data storage and logic circuitry that accounts for inaccuracies attributable to the plurality of comparator circuits by providing, for each comparator circuit, a set of calibration data indicative of the inaccuracies for adjusting comparison operations performed by the plurality of comparator circuits.

Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

A supply voltage supervisor circuit includes a comparator circuit. The comparator circuit includes a first input terminal, a second input terminal, a first transistor, and a second transistor. The first transistor has a first threshold voltage, and includes a first terminal coupled to the first input terminal. The second transistor has a second threshold voltage that is different from the first voltage threshold, and includes a first terminal coupled to the second input terminal, and a second terminal coupled to a second terminal of the first transistor. A trip point of the comparator circuit is based on a difference of the first threshold voltage and the second threshold voltage.

A supply voltage supervisor circuit includes a comparator circuit. The comparator circuit includes a first input terminal, a second input terminal, a first transistor, and a second transistor. The first transistor has a first threshold voltage, and includes a first terminal coupled to the first input terminal. The second transistor has a second threshold voltage that is different from the first voltage threshold, and includes a first terminal coupled to the second input terminal, and a second terminal coupled to a second terminal of the first transistor. A trip point of the comparator circuit is based on a difference of the first threshold voltage and the second threshold voltage.

A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs.

A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs.

A comparator circuit is implemented using a simple comparator core having two gain stages integrated in a single circuit block. The circuit operates with improved speed and resolution in comparison to a conventional continuous-time comparator. Offset trimming allows for the crossing time of the comparator to be adjusted close to an ideal crossing time.