A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.

A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.

A clock synthesis circuit and method provides for precision controlling and programming a selected number of clock pulses (or simply “clocks”) fitted within time periods between two consecutive pulses of a so-called system heartbeat (SHB) timing signal. The disclosed embodiments have applicability in light emitting diode (LED) display driver integrated circuits (ICs) and, more generally, digital circuits including computer processors, microcontrollers, logic devices such as field-programmable gate arrays (FP-GA), and other logic circuitry.

A clock synthesis circuit and method provides for precision controlling and programming a selected number of clock pulses (or simply “clocks”) fitted within time periods between two consecutive pulses of a so-called system heartbeat (SHB) timing signal. The disclosed embodiments have applicability in light emitting diode (LED) display driver integrated circuits (ICs) and, more generally, digital circuits including computer processors, microcontrollers, logic devices such as field-programmable gate arrays (FP-GA), and other logic circuitry.

The disclosure discloses an RC oscillating circuit. A first end of a capacitor is grounded, a second end of the capacitor is connected to a charging path, a discharging path and a comparator, A first input end of a comparator is connected to first reference voltage. An output end of the comparator outputs a first output signal and is connected to a control end of the discharging path. The first reference voltage provides the flipped voltage of the comparator The first output signal forms an output clock signal. A first regulating circuit is configured to regulate the magnitude of the charging current and realize coarse frequency tuning. A second regulating circuit is configured to regulate the magnitude of the first reference voltage and realize fine frequency tuning. The disclosure has the advantages of low power consumption, fast start, high precision and wide tuning range.

A comparator circuit configured to output an output voltage at a first logic level, upon an input voltage exceeding a first threshold voltage, and output the output voltage at a second logic level, upon the input voltage dropping below a second threshold voltage lower than the first threshold voltage. The comparator circuit includes a converter circuit configured to convert the input voltage of the comparator circuit into a first voltage and a second voltage lower than the first voltage, and a logic circuit configured to output a voltage, as the output voltage of the comparator circuit, that is at the first logic level, upon the first voltage exceeding a third threshold voltage, and at the second logic level, upon the second voltage dropping below a fourth threshold voltage lower than the third threshold voltage.

A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin. The control circuitry is further configured to selectively couple at least one of the second input pins and the reference input pin to the output pin during falling transitions of the pulsed output signal between two positive voltage levels, and selectively couple at least one of the first input pins and the reference input pin to the output pin during rising transitions of the pulsed output signal between two negative voltage levels.

A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin. The control circuitry is further configured to selectively couple at least one of the second input pins and the reference input pin to the output pin during falling transitions of the pulsed output signal between two positive voltage levels, and selectively couple at least one of the first input pins and the reference input pin to the output pin during rising transitions of the pulsed output signal between two negative voltage levels.

Some embodiments include a system comprising: an RF source configured to generate an RF signal; an RF frequency control circuit coupled to the RF source and configured to adjust a frequency of the RF signal; an accelerator structure configured to accelerate a particle beam in response to the RF signal; and control logic configured to: receive a plurality of settings over time for the RF source; adjust the RF signal in response to the settings; and adjust a setpoint of the RF frequency control circuit in response to the settings.

Some embodiments include a system comprising: an RF source configured to generate an RF signal; an RF frequency control circuit coupled to the RF source and configured to adjust a frequency of the RF signal; an accelerator structure configured to accelerate a particle beam in response to the RF signal; and control logic configured to: receive a plurality of settings over time for the RF source; adjust the RF signal in response to the settings; and adjust a setpoint of the RF frequency control circuit in response to the settings.