Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.

Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.

An adaptive feedback method for use in a memory device is provided. The memory device includes a first input-receiver circuit and a plurality of second input-receiver circuits. The method includes the steps of: providing a clock signal and an inverted clock signal to the first input-receiver circuit; generating an enable control signal by the first input-receiver circuit to control a first feedback path in the first input-receiver circuit; in response to the frequency of the clock signal and the inverted clock signal being higher than or equal to a predetermined frequency, activating the first feedback path in the first input-receiver circuit according to the enable control signal; and in response to the frequency of the clock signal and the inverted clock signal being lower than the predetermined frequency, deactivating the first feedback path in the first input-receiver circuit according to the enable control signal.

An adaptive feedback method for use in a memory device is provided. The memory device includes a first input-receiver circuit and a plurality of second input-receiver circuits. The method includes the steps of: providing a clock signal and an inverted clock signal to the first input-receiver circuit; generating an enable control signal by the first input-receiver circuit to control a first feedback path in the first input-receiver circuit; in response to the frequency of the clock signal and the inverted clock signal being higher than or equal to a predetermined frequency, activating the first feedback path in the first input-receiver circuit according to the enable control signal; and in response to the frequency of the clock signal and the inverted clock signal being lower than the predetermined frequency, deactivating the first feedback path in the first input-receiver circuit according to the enable control signal.

An example clock synthesizer, having a single-phase clock signal as input and generating an output clock, includes a phase decrementer configured to receive a fractional period value, configured to, responsive to the fractional period value, maintain a fractional count, and configured to accumulate residual phase from cycle-to-cycle of the output clock. A clock generator provides an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero. A clock phase selector is configured to provide a signal having a fractional portion of the fractional count. A phase generator and combiner is coupled to an output of the clock generator, and an output of the clock phase selector, and is configured to provide the output clock.

An example clock synthesizer, having a single-phase clock signal as input and generating an output clock, includes a phase decrementer configured to receive a fractional period value, configured to, responsive to the fractional period value, maintain a fractional count, and configured to accumulate residual phase from cycle-to-cycle of the output clock. A clock generator provides an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero. A clock phase selector is configured to provide a signal having a fractional portion of the fractional count. A phase generator and combiner is coupled to an output of the clock generator, and an output of the clock phase selector, and is configured to provide the output clock.

In an embodiment an oscillator circuit comprises a first integrator-comparator unit, a second integrator-comparator unit, and a logic circuit. The first integrator-comparator unit is prepared to provide a first signal as a function of a first integration of a first charging current and a subsequent comparison of a first integration signal resulting from the first integration with a reference signal. The second integrator-comparator unit is prepared to provide a third signal as a function of a second integration of a second charging current and a subsequent comparison of a second integration signal resulting from the second integration with the reference signal. The logic circuit is adapted to provide a clock signal, a first and a second measurement signal for respectively controlling the first and the second integrator-comparator unit.

In an embodiment an oscillator circuit comprises a first integrator-comparator unit, a second integrator-comparator unit, and a logic circuit. The first integrator-comparator unit is prepared to provide a first signal as a function of a first integration of a first charging current and a subsequent comparison of a first integration signal resulting from the first integration with a reference signal. The second integrator-comparator unit is prepared to provide a third signal as a function of a second integration of a second charging current and a subsequent comparison of a second integration signal resulting from the second integration with the reference signal. The logic circuit is adapted to provide a clock signal, a first and a second measurement signal for respectively controlling the first and the second integrator-comparator unit.

A clock synthesis circuit and method provides for precision controlling and programming a selected number of clock pulses (or simply clocks) fitted within time periods between two consecutive pulses of a so-called system heartbeat (SHB) timing signal. The disclosed embodiments have applicability in light emitting diode (LED) display driver integrated circuits (ICs) and, more generally, digital circuits including computer processors, microcontrollers, logic devices such as field-programmable gate arrays (FP-GA), and other logic circuitry.

A clock synthesis circuit and method provides for precision controlling and programming a selected number of clock pulses (or simply clocks) fitted within time periods between two consecutive pulses of a so-called system heartbeat (SHB) timing signal. The disclosed embodiments have applicability in light emitting diode (LED) display driver integrated circuits (ICs) and, more generally, digital circuits including computer processors, microcontrollers, logic devices such as field-programmable gate arrays (FP-GA), and other logic circuitry.