Some embodiments include a system comprising: a particle power source configured to generate a particle power signal; a radio frequency (RF) power source configured to generate an RF power signal; a particle source configured to generate a particle beam in response to the particle power signal; a RF source configured to generate an RF signal in response to the RF power signal; and an accelerator structure configured to accelerate the particle beam in response to the RF signal; wherein a timing of the RF power signal is different from a timing of the particle power signal.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.

In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.

The present invention relates to a remotely triggered improved electrical stimulus circuit to be worn by cattle that is lightweight and can store voltage lower than what is to be supplied to an animal. Known cattle electrical stimulus collars may be heavy, use a lot of energy, and not supply a consistent electrical stimulus. The present electrical stimulus circuit utilizes feedback loops to allow the use of high tolerance lightweight capacitors, and/or cool down periods to utilize a highly inefficient transformer running fully saturated.

A disclosed structure includes a section (e.g., an always on (AON) section) with at least one N-channel transistor (NFET) and at least one P-channel transistor (PFET). The structure further includes a switch with first and second inputs connected to receive positive and negative bias voltages, respectively, and first and second outputs connected to bias back gates of the NFET(s) and PFET(s), respectively, of the section. The structure is also configured to generate select signals for controlling the input-to-output connections established by the switch. In a power saving mode, these signals cause the switch to establish input-to-output connections resulting only in reverse back biasing of the NFET(s) and PFET(s) of the section. In a functional mode, these signals can cause the switch to establish input-to-output connections resulting in either forward back biasing or reverse back biasing. Also disclosed is a method of operating the structure.

A disclosed structure includes a section (e.g., an always on (AON) section) with at least one N-channel transistor (NFET) and at least one P-channel transistor (PFET). The structure further includes a switch with first and second inputs connected to receive positive and negative bias voltages, respectively, and first and second outputs connected to bias back gates of the NFET(s) and PFET(s), respectively, of the section. The structure is also configured to generate select signals for controlling the input-to-output connections established by the switch. In a power saving mode, these signals cause the switch to establish input-to-output connections resulting only in reverse back biasing of the NFET(s) and PFET(s) of the section. In a functional mode, these signals can cause the switch to establish input-to-output connections resulting in either forward back biasing or reverse back biasing. Also disclosed is a method of operating the structure.